Gsr Bit Definitions - Intel PXA255 Developer's Manual

AC'97 Controller Unit
Table 13-8. GSR Bit Definitions (Sheet 1 of 2)
Physical Address
4050_001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
31:20
19 CDONE
18 SDONE
17:16
15 RDCS
14 BIT3SLT12
13 BIT2SLT12
12 BIT1SLT12
11 SECRES
10 PRIRES
9
8
7 MINT
13-22
0 0 0 0 0 0 0
— reserved
Command Done (CDONE):
0 = ACUNIT has not sent command address and data to the CODEC.
1 = ACUNIT has sent command address and data to the CODEC.
This bit is cleared by software writing a '1' to this location (interruptible)
Status Done (SDONE):
0 = ACUNIT has not received status address and data from the CODEC.
1 = ACUNIT has received status address and data from the CODEC.
This bit is cleared by software writing a '1' to this location (interruptible)
— reserved
Read Completion Status:
This bit indicates the status of CODEC read completions.
0 = The CODEC read completed normally
1 = The CODEC read resulted in a timeout.
The bit remains set until cleared by software. This bit is cleared by software writing a '1' to
this location.
Bit 3 of slot 12:
Display Bit 3 of the most recent valid slot 12
Bit 2 of slot 12:
Display Bit 2 of the most recent valid slot 12
Bit 1 of slot 12:
Display Bit 1 of the most recent valid slot 12
Secondary Resume Interrupt:
0 = A resume event has not occurred on the SDATA_IN_1.
1 = A resume event occurred on the SDATA_IN_1.
This bit is cleared by software writing a '1' to this location (interruptible).
Primary Resume Interrupt:
0 = A resume event has not occurred on the SDATA_IN_0.
1 = A resume event occurred on the SDATA_IN_0.
This bit is cleared by software writing a '1' to this location (interruptible).
Secondary CODEC Ready (SCR)
SCR
Reflects the state of the CODEC ready bit in SDATA_IN_1 (interruptible)
Primary CODEC Ready (PCR)
PCR
Reflects the state of the CODEC ready bit in SDATA_IN_0 (interruptible)
Mic In Interrupt (MINT)
0 = None of the mic-in channel interrupts occurred.
1 = One of the mic-in channel interrupts occurred.
When the specific interrupt is cleared, this bit will be cleared (interruptible).
GSR Register
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
AC'97 Controller Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0