Ssp Data Register (Ssdr); Tft And Rft Values For Dma Servicing; Ssdr Bit Definitions - Intel PXA255 Developer's Manual

Table 8-4. TFT and RFT Values for DMA Servicing
DMA Burst Size
8 Bytes
16 Bytes
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
8.7.3

SSP Data Register (SSDR)

SSDR, shown in
transfers. Transfers can be single transfers, 4 half-word bursts, or 8 half-word bursts.
As the system accesses the register, FIFO control logic transfers data automatically between
register and FIFO as fast as the system moves data. The SSP Status Register has bits that indicate
whether either FIFO is full, above/below a programmable threshold, or empty.
For transmit operations from SSPC to SSP peripheral, the CPU (using programmed I/O) may write
to the SSDR when the transmit FIFO is below its threshold level.
When a data size less than 16-bits is selected, do not left-justify data before it is written to the
SSDR. Transmit logic left-justifies the data and ignores any unused bits. Received data less than
16-bits is automatically right-justified in the receive FIFO.
When the SSPC is programmed for National Microwire frame format and the size for transmit data
is 8-bits, as selected by the MWDS bit in the SSCR1, the most significant byte is ignored.
SSCR0[DSS] controls receive data size.
Note: Both FIFOs are cleared when the SSPC is reset or a zero is written to the SSCR0[SSE] bit.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 8-5. SSDR Bit Definitions
0x4100_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset
Bits Name
15:0 Data
(Low Word)
31:16 —
Intel® PXA255 Processor Developer's Manual
TFT Value RFT Value
Min Max Min Max
0 11 3 15
0 7 7 15
Table 8-5, is a single address location that can be accessed by read/write data
SSP Data Register (SSDR)
reserved
X
Data word to be written to/read from Transmit/Receive FIFO
reserved
Synchronous Serial Port Controller
Synchronous Serial Port Controller
8 7 6
Transmit/Receive Data
0x0000
Description
5 4 3 2 1 0
8-15