Contents
9.3
Functional Description .......................................................................................................9-1
9.3.1
Operational Blocks................................................................................................9-3
9.3.2
9.3.3
9.4
I2C Bus Operation .............................................................................................................9-7
9.4.1
9.4.2
9.4.3
I2C Acknowledge..................................................................................................9-8
9.4.4
Polling ...................................................................................................................9-9
9.4.5
Arbitration .............................................................................................................9-9
9.4.6
Master Operations ..............................................................................................9-12
9.4.7
Slave Operations ................................................................................................9-14
9.4.8
General Call Address..........................................................................................9-16
9.5
9.5.1
Initialize Unit .......................................................................................................9-18
9.5.2
9.5.3
9.6
9.6.1
Initialize Unit .......................................................................................................9-19
9.6.2
9.6.3
9.6.4
9.6.5
9.7
Glitch Suppression Logic .................................................................................................9-21
9.8
Reset Conditions .............................................................................................................9-21
9.9
Register Definitions..........................................................................................................9-22
9.9.1
I2C Bus Monitor Register (IBMR) .......................................................................9-22
9.9.2
I2C Data Buffer Register (IDBR).........................................................................9-22
9.9.3
9.9.4
9.9.5
I2C Slave Address Register (ISAR)....................................................................9-27
10
UARTs ........................................................................................................................................10-1
10.1
Feature List......................................................................................................................10-1
10.2
Overview..........................................................................................................................10-2
10.2.2 Bluetooth UART..................................................................................................10-2
10.2.3 Standard UART ..................................................................................................10-2
10.3
Signal Descriptions ..........................................................................................................10-3
10.4
10.4.1 Reset ..................................................................................................................10-5
10.4.5 DMA Requests..................................................................................................10-22
10.5
UART Register Summary ..............................................................................................10-26
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Intel® PXA255 Processor Developer's Manual