Operational Blocks; I2C Bus Interface Modes; Modes Of Operation - Intel PXA255 Developer's Manual

9.3.1

Operational Blocks

2
The I C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to
notify the CPU that there is activity on the I
2
I C unit consists of the two wire interface to the I
from the processor, a set of control and status registers, and a shift register for parallel/serial
conversions.
2
The I C unit initiates an interrupt to the processor when a buffer is full, a buffer is empty, the I
unit slave address is detected, arbitration is lost, or a bus error condition occurs. All interrupt
conditions must be cleared explicitly by software. See
The 8-bit I
interface to the I
The serial shift register is not user accessible.
2
The I C Control Register (ICR) and the I
mapped address space. The registers and their functions are defined in
2
The I C unit supports a fast mode operation of 400 Kbits/sec and a standard mode of 100 Kbits/sec.
Refer to The I
2
9.3.2 I C Bus Interface Modes
2
The I C unit can accomplish a transfer in different operation modes.
different modes.
Table 9-3. Modes of Operation
Master - Transmit
Master - Receive
Slave - Transmit
Slave - Receive (default)
While the I
bus and receive any slave addresses intended for the processor.
Intel® PXA255 Processor Developer's Manual
2
C Data Buffer Register (IDBR) is loaded with a byte of data from the shift register
2
C bus when receiving data and from the processor internal bus when writing data.
2
C-Bus Specification for details.
Mode
• I
• Used for a write operation.
• I
• I
• Slave device in slave-receive mode
• I
• Used for a read operation.
• I
• I
• Slave device in slave-transmit mode
• I
• Used for a master read operation.
• I
• Master device in master-receive mode.
• I
• Used for a master write operation.
• I
• Master device in master-transmit mode.
2
C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the
2
C bus. Polling can be used instead of interrupts. The
2
C bus, an 8-bit buffer for passing data to and
Section 9.9.4
2
C Status Register (ISR) are located in the I
Description
2
C unit acts as a master.
2
C unit sends the data.
2
C unit is responsible for clocking.
2
C unit acts as a master.
2
C unit receives the data.
2
C unit is responsible for clocking.
2
C unit acts as a slave.
2
C unit sends the data.
2
C unit acts as a slave.
2
C unit receives the data.
2
I C Bus Interface Unit
for details.
2
C memory-
Section 9.9.
Table 9-3 summarizes the
2
C
9-3