Udc Endpoint X Data Register (Uddr5/10/15); Usb Device Controller Register Summary; Uddr4/9/14 Bit Definitions; Uddr5/10/15 Bit Definitions - Intel PXA255 Developer's Manual

USB Device Controller
Table 12-31. UDDR4/9/14 Bit Definitions
0x 4060_0400
0x 4060_0900
0x 4060_0E00
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset x x x x x x
Bits Name
31:8
7:0 DATA
12.6.21

UDC Endpoint x Data Register (UDDR5/10/15)

UDDR5/10/15, shown in
loaded via direct Megacell writes. Because the USB system is a host initiator model, the host must
poll Endpoint 5 to determine interrupt conditions. The UDC can not initiate the transaction.
Table 12-32. UDDR5/10/15 Bit Definitions
0x 4060_00A0
0x 4060_00C0
0x 4060_00E0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset x x x x x x
Bits Name
31:8
7:0 DATA
12.7

USB Device Controller Register Summary

Table 12-33
them.
Table 12-33. USB Device Controller Register Summary (Sheet 1 of 3)
Address
0x4060_0000
0x4060_0004
0x4060_0008
0x4060_000C
12-48
reserved
x x x x x x x
— reserved
Top of endpoint data currently being loaded
Table 12-32, is an interrupt IN endpoint that is 8 bytes deep. Data must be
reserved
x x x x x x x
— reserved
Top of endpoint data currently being loaded
shows the registers associated with the UDC and the physical addresses used to access
Name
UDCCR
—
UDCCFR
—
UDDR4
UDDR9
UDDR14
x x x x x x x x
Description
UDDR5
UDDR10
UDDR15
x x x x x x x x
Description
Description
UDC Control Register
reserved for future use
UDC Control Function Register
reserved for future use
Intel® PXA255 Processor Developer's Manual
USB Device Controller
8 7 6 5 4 3
8-bit Data
x x x 0 0 0 0 0
USB Device Controller
8 7 6 5 4 3
8-bit Data
x x x 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0