Reset Controller Status Register (Rcsr); Pgsr2 Bit Definitions - Intel PXA255 Developer's Manual

Table 3-18. PGSR2 Bit Definitions
0x40F0_0028
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0
Bits
[31:17]
[16:0]
3.5.11

Reset Controller Status Register (RCSR)

The CPU uses the RCSR, shown in
processor can be reset in four ways:
•
Hardware reset
•
Watchdog reset
•
Sleep mode
•
GPIO reset
Refer to Table 2-4, "Effect of Each Type of Reset on Internal Register State" on page 2-6
of the behavior of different modules during each type of reset.
Each RCSR status bit is set by a different reset source and can be cleared by writing a 1 back to the
bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset
state of zero.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
0 0 0 0 0 0 0 0
Name
— reserved
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
SSx
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
PGSR2
0 0 0 0 0 0 0 0
Description
Table 3-19, to determine a reset's last cause or causes. The
Clocks and Power Manager
Clocks and Power Manager
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
for details
3-33