Expansion Card External Logic For A One-Socket Configuration - Intel PXA255 Developer's Manual

Figure 6-27. Expansion Card External Logic for a One-Socket Configuration
Intel® - PXA255 Processor
MD<15:0>
RD/nWR
GPIO<w>
GPIO<x>
PSKTSEL
GPIO<y>
GPIO<z>
MA[25:0]
nPWE
nPREG
nPCE<2:1>
nPOE
nPIOR
nPIOW
nPWAIT
nIOIS16
Figure 6-28
through a buffer to two separate GPIO pins. In the data bus transceiver control logic, nPCE1
controls the enable for the low byte lane and nPCE2 controls the enable for the high byte lane.\
Intel® PXA255 Processor Developer's Manual
nPCD0
nPCD1
PRDY_BSY0
PADDR_EN0
shows the glue logic need for a 2-socket system. RDY/nBSY signals are routed
DIR nOE
5V to 3.3V or 2.5V
5V to 3.3V or 2.5V
Memory Controller
Socket 0
D<15:0>
nCD<1>
nCD<2>
RDY/nBSY
A[25:0]
nWE
nREG
nCE<2:1>
nOE
nIOR
nIOW
nWAIT
nIOIS16
6-67