Coprocessor 15 Register 1 - P-Bit; Id Bit Definitions; Pxa255 Processor Id Values - Intel PXA255 Developer's Manual

System Architecture
Table 2-2. ID Bit Definitions
CP15 Register 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 1 1 0 1
[31:24]
[23:16]
[15:13]
[12:10]
[9:4]
[3:0]
Table 2-3. PXA255 Processor ID Values
Stepping
A0
2.2.5

Coprocessor 15 Register 1 - P-Bit

Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not
implemented in the processor and must be written as zero. Similarly, the P-bit in the page table
descriptor in the MMU is not implemented and must be written to zero.
2-4
0 0 1 0 0 0 0 0
Implementation Implementation trademark.
–
Trademark 0x69
Architecture ARM* Architecture version of the core.
–
Version 0x05
This field is updated when new sets of features are added to the core. This
allows software that is dependant on core features to target a specific core.
Core Generation
Core generation:
0b001
This field is updated each time a core is revised. Differences may include
errata, software workarounds, etc.
Core revision:
Core Revision
0b000
0b010
0b011
Product Number
Product Number
0b010000 – PXA255 processor
This field tracks the different steppings for each ASSP.
Product Revision Product Revision
0b0110
ARM ID
0x6905_2D06
ID
1 0 1 0 0 1 0 0
Intel® Corporation.
ARM* Architecture version 5TE
–
Intel XScale® core
–
First version of the core.
–
Third version of the core.
–
Fourth version of the core.
–
A0 Stepping
JTAG ID
0x6926_4013
Intel® PXA255 Processor Developer's Manual
CP15
8 7 6 5 4 3
0 0 1 0 0 0 0 0
2 1 0
0 0 0