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USB Device Controller
Table 12-27. UDDR0 Bit Definitions
0x 4060_0080
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset
x
x
x
x
x
x
Bits
Name
31:8
7:0
DATA
12.6.17
UDC Endpoint x Data Register (UDDR1/6/11)
UDDR1/6/11, shown in
Data can be loaded via DMA or direct core writes. Because it is double buffered, up to two packets
of data may be loaded for transmission.
These are write-only registers. Write zeros to reserved bits.
Table 12-28. UDDR1/6/11 Bit Definitions
0x 4060_0100
0x 4060_0600
0x 4060_0B00
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset
x
x
x
x
x
x
Bits
Name
31:8
7:0
DATA
12.6.18
UDC Endpoint x Data Register (UDDR2/7/12)
UDDR2/7/12, shown in
deep. The UDC will generate either an interrupt or DMA request as soon as the EOP is received.
Since it is double buffered, up to two packets of data may be ready. Via DMA or by direct read
from the core, the data can be removed from the UDC. If one packet is being removed and the
packet behind it has already been received, the UDC will issue a NAK to the host the next time it
sends an OUT packet to endpoint(x). This NAK condition will remain in place until a full packet
space is available in the UDC at Endpoint(x).
12-46
reserved
x
x
x
x
x
x
x
—
reserved
Top/bottom of endpoint 0 FIFO data.
Read – Bottom of endpoint 0 FIFO data.
Write – Top of endpoint 0 FIFO data.
Table
12-28, is a double-buffered bulk IN endpoint that is 64 bytes deep.
reserved
x
x
x
x
x
x
x
—
reserved
Top of endpoint data currently being loaded
Table
12-29, is a double-buffered bulk OUT endpoint that is 64 bytes
UDDR0
x
x
x
x
x
x
x
x
Description
UDDR1
UDDR6
UDDR11
x
x
x
x
x
x
x
x
Description
Intel® PXA255 Processor Developer's Manual
USB Device Controller
8
7
6
5
4
3
Bottom of Endpoint 0 FIFO
(for Reads) Top of
Endpoint 0 FIFO (for
Writes)
x
x
x
0
0
0
0
0
USB Device Controller
8
7
6
5
4
3
8-Bit Data
x
x
x
x
x
0
0
0
2
1
0
0
0
0
2
1
0
0
0
0
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