Pin & Signal Descriptions For The Pxa255 Processor - Intel PXA255 Developer's Manual

Table 2-5. Processor Pin Types
Type
IA
OA
IAOA
SUP
Table 2-6
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin Name Type
Memory Controller Pins
MA[25:0] OCZ
MD[15:0] ICOCZ
MD[31:16] ICOCZ
nOE OCZ
nWE OCZ
nSDCS[3:0] OCZ
DQM[3:0] OCZ
nSDRAS OCZ
nSDCAS OCZ
SDCKE[0] OC
SDCKE[1] OC
SDCLK[0] OC
Intel® PXA255 Processor Developer's Manual
Analog Input
Analog output
Analog bidirectional
Supply pin (either VCC or VSS)
describes the PXA255 processor pins.
Signal Descriptions
Memory address bus. (output) Signals the address
requested for memory accesses.
Memory data bus. (input/output) Lower 16 bits of the
data bus.
Memory data bus. (input/output) Used for 32-bit
memories.
Memory output enable. (output) Connect to the output
enables of memory devices to control data bus drivers.
Memory write enable. (output) Connect to the write
enables of memory devices.
SDRAM CS for banks 3 through 0. (output) Connect to
the chip select (CS) pins for SDRAM. For the PXA255
processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.
SDRAM DQM for data bytes 3 through 0. (output)
Connect to the data output mask enables (DQM) for
SDRAM.
SDRAM RAS. (output) Connect to the row address
strobe (RAS) pins for all banks of SDRAM.
SDRAM CAS. (output) Connect to the column address
strobe (CAS) pins for all banks of SDRAM.
Synchronous Static Memory clock enable. (output)
Connect to the CKE pins of SMROM. The memory
controller provides control register bits for deassertion.
SDRAM and/or Synchronous Static Memory clock
enable. (output) Connect to the clock enable pins of
SDRAM. It is deasserted during sleep. SDCKE[1] is
always deasserted upon reset. The memory controller
provides control register bits for deassertion.
Synchronous Static Memory clock. (output) Connect to
the clock (CLK) pins of SMROM. It is driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[0] control register assertion bit
defaults to on if the boot-time static memory bank 0 is
configured for SMROM.
Function
Driven Low
Hi-Z
Hi-Z
Driven High
Driven High
Driven High
Driven Low
Driven High
Driven High
Driven Low
Driven Low
System Architecture
Reset State Sleep State
Driven Low
Driven Low
Driven Low
Note [4]
Note [4]
Note [5]
Driven Low
Driven High
Driven High
Driven Low
Driven Low
2-9