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Intel Pentium Pro Family Developer's Manual

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Pentium
Pro Family
Developer's Manual
Volume 1:
Specifications
®
NOTE: The Pentium
Pro Family Developer's Manual consists of three
books: Specifications, Order Number 242690; Programmer's Reference
Manual, Order Number 242691; and the Operating System Writer's Guide,
Order Number 242692.
Please refer to all three volumes when evaluating your design needs.
1996

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Summary of Contents for Intel Pentium Pro Family

  • Page 1 ® Pentium Pro Family Developer’s Manual Volume 1: Specifications ® NOTE: The Pentium Pro Family Developer’s Manual consists of three books: Specifications, Order Number 242690; Programmer’s Reference Manual, Order Number 242691; and the Operating System Writer’s Guide, Order Number 242692. Please refer to all three volumes when evaluating your design needs.
  • Page 2 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.

  • Page 3: Table Of Contents

    TABLE OF CONTENTS PAGE CHAPTER 1 COMPONENT INTRODUCTION 1.1. BUS FEATURES ........... 1-2 1.2.
  • Page 4 TABLE OF CONTENTS PAGE CHAPTER 4 BUS PROTOCOL 4.1. ARBITRATION PHASE ..........4-1 4.1.1.
  • Page 5 TABLE OF CONTENTS PAGE 4.4.3.2. Valid Snoop Phase ..........4-25 4.4.3.3.
  • Page 6 TABLE OF CONTENTS PAGE 5.2.3.5. Branch Trace Message......... . . 5-9 5.2.3.6.
  • Page 7 TABLE OF CONTENTS PAGE 8.2.4. Time-out Errors ..........8-6 8.2.5.
  • Page 8 TABLE OF CONTENTS PAGE 10.4.3. BIST Result Boundary Scan Register ....... . . 10-9 10.4.4.
  • Page 9 TABLE OF CONTENTS PAGE CHAPTER 13 3.3V TOLERANT SIGNAL QUALITY SPECIFICATIONS 13.1. OVERSHOOT/UNDERSHOOT GUIDELINES ......13-1 13.2.
  • Page 10 TABLE OF CONTENTS PAGE ® 17.2.3. OverDrive Voltage Regulator Module Definition ......17-8 ® 17.2.3.1. OverDrive VRM Requirement ........17-8 ®...
  • Page 11 TABLE OF CONTENTS PAGE A.1.5. AP[1:0]# (I/O) ........... . A-4 A.1.6.
  • Page 12 TABLE OF FIGURES PAGE Figure 1-1. The Pentium ® Pro Processor Integrating the CPU, L2 Cache, APIC and Bus Controller......... . 1-1 Figure 1-2.
  • Page 13 TABLE OF FIGURES PAGE ® Figure 10-4. Operation of the Pentium Pro Processor TAP Instruction Register..10-5 Figure 10-5. TAP Instruction Register Access ....... . . 10-6 Figure 11-1.
  • Page 14 TABLE OF FIGURES PAGE ® Figure 16-7. Pentium Pro Processor-Based System Where Boundary Scan is Not Used........... .16-10 ®...
  • Page 15 TABLE OF TABLES ® Table 3-1. Burst Order Used For Pentium Pro Processor Bus Line Transfers..3-9 Table 3-2. Execution Control Signals........3-10 Table 3-3.
  • Page 16 TABLE OF TABLES Table 11-12. GTL+ Signal Groups Ringback Tolerance ......11-20 Table 11-13. 3.3V Tolerant Signal Groups A.C. Specifications .....11-20 Table 11-14.

  • Page 17: Component Introduction

    Component Introduction...

  • Page 18: Figure 1-1. The Pentium ® Pro Processor Integrating The Cpu, L2 Cache

    8086/88, 80286, Intel386, Intel486, and Pentium processors. The Pentium Pro processor integrates the second level cache, the APIC, and the memory bus controller found in previous Intel processor families into a single component, as shown in Figure 1-1.

  • Page 19: Bus Features

    COMPONENT INTRODUCTION family systems which are integrated into this single component. This integration results in the Pentium Pro processor bus more closely resembling a symmetric multi-processing (SMP) sys- tem bus rather than a previous generation processor-to-cache bus. This added level of integration and improved performance results in higher power consumption and a new bus technology.

  • Page 20: Bus Description

    COMPONENT INTRODUCTION The ratio clock approach reduces the tight coupling between the processor clock and the external bus clock. For a fixed system bus clock frequency, Pentium Pro processors introduced later with higher processor clock frequencies can use the same support chip-set at the same bus frequency. An investment in a Pentium Pro processor chip-set is protected for a longer time and for a greater range of processor frequencies.

  • Page 21: System Design Aspects

    COMPONENT INTRODUCTION 1.2.1. System Design Aspects The Pentium Pro processor bus clock and the Pentium Pro processor internal execution clock run at different frequencies, related by a ratio. Section 9.2., “Clock Frequencies and Ratios” pro- vides more information about bus frequency and processor frequency. The Pentium Pro processor bus uses GTL+.

  • Page 22: Data Integrity

    COMPONENT INTRODUCTION 1.2.4. Data Integrity The Pentium Pro processor bus provides parity signals for address, request, and response sig- nals. The bus protocol supports retrying bus requests. The Pentium Pro processor bus supports error correcting code (ECC) on the data bus and has correction capability at the receiver.

  • Page 23: Terminology Clarification

    COMPONENT INTRODUCTION Up to four Pentium Pro processors can be gluelessly interconnected on the Pentium Pro proces- sor bus. These agents are bus masters, capable of supporting all the features described in this document. The interface to the remainder of the system is represented by the high-speed I/O in- terface and memory interface blocks.
  • Page 24 COMPONENT INTRODUCTION Snooping Agent. A caching bus agent that observes (“snoops”) bus transactions to • maintain cache coherency. Responding Agent. The agent that provides the response on the RS[2:0]# signals to the • transaction. Typically the addressed agent. Each transaction has several phases that include some or all of the following phases. Arbitration Phase.

  • Page 25: Compatibility Note

    COMPONENT INTRODUCTION 1.5. COMPATIBILITY NOTE In this document, some register bits are Intel Reserved. When reserved bits are documented, treat them as fully undefined. This is essential for software compatibility with future processors. Follow the guidelines below: 1. Do not depend on the states of any undefined bits when testing the values of defined register bits.

  • Page 26: Pentium ® Pro Processor Architecture Overview

    ® Pentium Processor Architecture Overview...

  • Page 28: Figure 2-1. Three Engines Communicating Using An Instruction Pool

    CHAPTER 2 ® PENTIUM PRO PROCESSOR ARCHITECTURE OVERVIEW The Pentium Pro processor has a decoupled, 12-stage, superpipelined implementation, trading less work per pipestage for more stages. The Pentium Pro processor also has a pipestage time 33 percent less than the Pentium processor, which helps achieve a higer clock rate on any given process.

  • Page 29: Full Core Utilization

    The sparse register set of an Intel Architecture (IA) processor will create many false dependencies on registers so the dispatch/ex- ecute unit will rename the IA registers into a larger register set to enable additional forward progress.

  • Page 30: The Pentium ® Pro Processor Pipeline

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW ® 2.2. THE PENTIUM PRO PROCESSOR PIPELINE In order to get a closer look at how the Pentium Pro processor implements Dynamic Execution, Figure 2-3 shows a block diagram including cache and memory interfaces. The “Units” shown in Figure 2-3 represent stages of the Pentium Pro processor pipeline.

  • Page 31: The Fetch/Decode Unit

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW • The FETCH/DECODE unit: An in-order unit that takes as input the user program instruction stream from the instruction cache, and decodes them into a series of micro- operations (µops) that represent the dataflow of that instruction stream. The pre-fetch is speculative.

  • Page 32: The Dispatch/Execute Unit

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW The ICache is a local instruction cache. The Next_IP unit provides the ICache index, based on inputs from the Branch Target Buffer (BTB), trap/interrupt status, and branch-misprediction in- dications from the integer execution section. The ICache fetches the cache line corresponding to the index from the Next_IP, and the next line, and presents 16 aligned bytes to the decoder.

  • Page 33: Figure 2-5. Inside The Dispatch/Execute Unit

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW RS - Reservation Station EU - Execution Unit FEU - Floating Point EU Port 0 IEU - Integer EU JEU - Jump EU To/from AGU - Address Generation Unit ROB - ReOrder Buffer Instruction Port 1 Pool (ROB) Port 2 Load...

  • Page 34: The Retire Unit

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW 2.2.3. The Retire Unit Figure 2-6 shows a more detailed view of the Retire Unit. To/from DCache RS - Reservation Station MIU - Memory Interface Unit RRF - Retirement Register File From Instruction Pool Figure 2-6. Inside the Retire Unit The retire unit is also checking the status of µops in the instruction pool.

  • Page 35: Architecture Summary

    PENTIUM® PRO PROCESSOR ARCHITECTURE OVERVIEW MOB - Memory Order Buffer AGU - Address Generation Unit Sys Mem ROB - ReOrder Buffer L2 Cache DCache To/from Instruction From Pool (ROB) Figure 2-7. Inside the Bus Interface Unit There are two types of memory access: loads and stores. Loads only need to specify the memory address to be accessed, the width of the data being retrieved, and the destination register.

  • Page 36: Bus Overview

    Bus Overview...

  • Page 37: Signal And Diagram Conventions

    CHAPTER 3 BUS OVERVIEW This chapter provides an overview of the Pentium Pro processor bus protocol, transactions, and bus signals. The Pentium Pro processor supports two other synchronous busses, APIC and JTAG. It also has PC compatibility signals and implementation specific signals. This chapter provides a functional description of the Pentium Pro processor bus only.

  • Page 38: Signaling On The Pentium Pro Processor Bus

    BUS OVERVIEW When signal values are referenced in tables, a 0 indicates inactive and a 1 indicates active. 0 and 1 do not reflect voltage levels. Remember, a # after a signal name indicates active low. An entry of 1 for ADS# means that ADS# is active, with a low voltage level. ®...

  • Page 39: Figure 3-1. Latched Bus Protocol

    BUS OVERVIEW Full clock allowed Full clock allowed for signal propagation for logic delays BCLK Assert A# Latch B# Latch A# Assert B# Figure 3-1. Latched Bus Protocol Any signal names that appear in brackets {} are internal signals only, and are not driven to the bus.

  • Page 40: Pentium ® Pro Processor Bus Protocol Overview

    BUS OVERVIEW ® 3.3. PENTIUM PRO PROCESSOR BUS PROTOCOL OVERVIEW Bus activity is hierarchically organized into operations, transactions, and phases. An operation is a bus procedure that appears atomic to software even though it may not be atom- ic on the bus. An operation may consist of a single bus transaction, but sometimes may involve multiple bus transactions or a single transaction with multiple data transfers.
  • Page 41 BUS OVERVIEW 10 11 12* 13 AAAA AAAA BCLK AAAA AAAA AAAA A A AA A A AAAA A A AA A A AAAAAAAA A A AAAA A A AAAA A A AAAA A A AAAA AAAAA AAAA AA A AAAA A A AAAA AA A AAAA A A AAAA...

  • Page 42: Bus Transaction Pipelining And Transaction Tracking

    BUS OVERVIEW Deferred • Retry • If the transaction does not have a Data Phase, that transaction is complete after the Response Phase. If the request agent has write data to transfer or is requesting read data, the transaction has a Data Phase which may extend beyond the Response Phase. Not all transactions contain all phases, not all phases occur in order, and some phases can be overlapped.

  • Page 43: Bus Transactions

    BUS OVERVIEW Other, agent specific, bus information must be tracked as well. Note that not every agent needs to track all of this additional information. Examples of additional information that might be tracked follow. Request agents (agents that issue transactions) might track: How many more transactions this agent can still issue? •...

  • Page 44: Data Transfers

    I/O ports and always deassert A[35:17]#. A16# is zero except when the first three bytes above the 64KByte address space are accessed (I/O wraparound). This is required for com- patibility with previous Intel processors. The Pentium Pro processor bus distinguishes between different transfer lengths.

  • Page 45: Line Transfers

    BUS OVERVIEW 3.3.4.1. LINE TRANSFERS A line transfer reads or writes a cache line, the unit of caching in a Pentium Pro processor sys- tem. On the Pentium Pro processor this is 32 bytes aligned on a 32-byte boundary. While a line is always aligned on a 32-byte boundary, a line transfer need not begin on that boundary.

  • Page 46: Signal Overview

    BUS OVERVIEW The Pentium Pro processor converts non-cacheable misaligned memory accesses that cross 8- byte boundaries into two partial transfers. For example, a non-cacheable, misaligned 8-byte read requires two Read Data Partial transactions. Similarly, the Pentium Pro processor converts I/O write accesses that cross 4-byte boundaries into 2 partial transfers.
  • Page 47 BUS OVERVIEW The INIT# input signal resets all Pentium Pro processor bus agents without affecting their inter- nal (L1 or L2) caches or their floating-point registers. Each Pentium Pro processor begins exe- cution at the address vector as defined during power on configuration. INIT# has another meaning on RESET#’s active to inactive transition: if INIT# is sampled active on RESET#’s ac- tive to inactive transition, then the Pentium Pro processor executes its built-in self test (BIST).

  • Page 48: Arbitration Phase Signals

    BUS OVERVIEW 3.4.2. Arbitration Phase Signals This signal group is used to arbitrate for the bus. Table 3-3. Arbitration Phase Signals Pin/Signal Name Pin Mnemonic Signal Mnemonic Number Symmetric Agent Bus Request BR[3:0]# BREQ[3:0]# Priority Agent Bus Request BPRI# BPRI# Block Next Request BNR# BNR#...

  • Page 49: Request Signals

    BUS OVERVIEW 3.4.3. Request Signals The request signals transfer request information, including the transaction address. A Request Phase is two clocks long beginning with the assertion of ADS#, the Address Strobe signal, as shown in Table 3-4. Table 3-4. Request Signals Pin Name Pin Mnemonic Signal Name...

  • Page 50: Table 3-5. Transaction Types Defined By Reqa#/Reqb# Signals

    BUS OVERVIEW Table 3-5. Transaction Types Defined by REQa#/REQb# Signals REQa[4:0]# REQb[4:0]# Transaction Deferred Reply Rsvd (Ignore) Interrupt Acknowledge DSZ# Special Transactions DSZ# Rsvd (Central agent response) DSZ# Branch Trace Message DSZ# Rsvd (Central agent response) DSZ# Rsvd (Central agent response) DSZ# I/O Read DSZ#...

  • Page 51: Table 3-6. Address Space Size

    BUS OVERVIEW Table 3-6. Address Space Size ASZ[1:0]# Memory Address Space Observing Agents 32-bit 32 & 36 bit agents 36-bit 36 bit agents only Reserved None Reserved None If the memory access is within the 0-to-(4GByte -1) address space, ASZ[1:0]# must be 00B. If the memory access is within the 4Gbyte-to-(64GByte -1) address space, ASZ[1:0]# must be 01B.

  • Page 52: Table 3-8. Memory Range Register Signal Encoding

    BUS OVERVIEW The ATTR[7:0]# pins describe the cache attributes. They are driven based on the Memory Type Range Register attributes and the Page Table attributes as described in Table 3-8. See Chapter 6, Range Registers for a description of the memory types. Table 3-8.

  • Page 53: Table 3-10. Special Transaction Encoding On Byte Enables

    BUS OVERVIEW Table 3-10. Special Transaction Encoding on Byte Enables Special Transaction Byte Enables[7:0]# Shutdown 0000 0001 Flush 0000 0010 Halt 0000 0011 Sync 0000 0100 Flush Acknowledge 0000 0101 Stop Grant Acknowledge 0000 0110 SMI Acknowledge 0000 0111 Reserved all other encodings The Extended Functions, EXF[4:0]#, supported are listed in Table 3-11.

  • Page 54: Error Phase Signals

    BUS OVERVIEW 3.4.4. Error Phase Signals The Error Phase signal group (see Table 3-12) contains signals driven in the Error Phase. This phase is one clock long and always begins three clocks after the Request Phase begins (3 clocks after ADS# is asserted). Table 3-12.

  • Page 55: Table 3-13. Snoop Signals

    BUS OVERVIEW Table 3-13. Snoop Signals Type Signal Names Number Keeping a Non-Modified Cache Line HIT# Hit to a Modified Cache Line HITM# Defer Transaction Completion DEFER# On observing a Request Phase (ADS# active) for a memory access, all caching agents are re- quired to perform an internal snoop operation and appropriately return HIT# and HITM# in the Snoop Phase.

  • Page 56: Response Signals

    BUS OVERVIEW later time; a retry response, implying that the transaction should be retried; or a hard error response. HITM# overrides DEFER# to determine the response type. DEFER# may still affect a locked operation. See Chapter 5, Bus Transactions and Operations for details. The requesting agent observes HIT#, HITM#, and DEFER# to determine the line’s final state in its cache.

  • Page 57: Data Phase Signals

    BUS OVERVIEW Table 3-15. Transaction Response Encodings RS2# RS1# RS0# Description and Required Snoop Result Idle state. (The RS[2:0]# pins must be driven inactive after being sampled asserted) Retry response. Deferred response. The data bus is used only by a writing agent. Reserved.

  • Page 58: Error Signals

    BUS OVERVIEW DRDY# indicates that valid data is on the bus and must be latched. The data bus owner asserts DRDY# for each clock in which valid data is to be transferred. DRDY# can be deasserted to insert wait states in the Data Phase. DBSY# is used to hold the bus before the first DRDY# and between DRDY# assertions for a multiple clock data transfer.

  • Page 59: Compatibility Signals

    BIST action, then it keeps FRCERR asserted for less than 20 clocks and then deasserts it. 3.4.9. Compatibility Signals The compatibility signals group (see Table 3-18) contains signals defined for compatibility with- in the Intel architecture processor family. Table 3-18. PC Compatibility Signals Type Signal Names Number...

  • Page 60: 3.4.10. Diagnostic Signals

    BUS OVERVIEW The Pentium Pro processor asserts FERR# when it detects an unmasked floating-point error. FERR# is included for compatibility with systems using DOS-type floating-point error reporting. If the IGNNE# input signal is asserted, the Pentium Pro processor ignores a numeric error and continues to execute non-control floating-point instructions.

  • Page 61: 3.4.11. Power, Ground, And Reserved Pins

    BUS OVERVIEW The diagnostic signals group shown in Table 3-19 provides signals for probing the Pentium Pro processor, monitoring Pentium Pro processor performance, and implementing an IEEE 1149.1 boundary scan. PM[1:0]# are the Performance Monitor signals. These signals are outputs from the Pentium Pro processor that indicate the status of four programmable counters for monitoring Pentium Pro processor performance.

  • Page 62: Bus Protocol

    Bus Protocol...

  • Page 63: Arbitration Phase

    CHAPTER 4 BUS PROTOCOL This chapter describes the protocol followed by bus agents in a transaction’s six phases. The phases are: Arbitration Phase • Request Phase • Error Phase • Snoop Phase • Response Phase • Data Phase • 4.1. ARBITRATION PHASE A bus agent must have bus ownership before it can initiate a transaction.

  • Page 64: Bus Signals

    BUS PROTOCOL Besides the two classes of arbitration agents, each bus agent has two actions available that act as arbitration modifiers: the bus lock and the request stall. The bus lock action is available to the current symmetric owner to block other agents, including the priority agent from acquiring the bus.

  • Page 65: Internal Bus States

    BUS PROTOCOL Priority Agent BPRI# Agent 2 Agent 3 Agent 0 Agent 1 BREQ0# BREQ1# BREQ2# System Interface Logic BREQ3# During Reset Figure 4-1. BR[3:0]# Physical Interconnection 4.1.3. Internal Bus States In order to maintain a glueless MP interface, some bus state is distributed and must be tracked by all agents on the bus.

  • Page 66: Agent Id

    BUS PROTOCOL symmetric agent currently owns the bus (“idle” state). The Pentium Pro processor will enter the idle state after AERR#, BINIT# and RESET#. The notion of idle state enables a shorter, two- clock arbitration latency from bus request to its ownership. The notion of busy state enables bus parking but increases arbitration latency to a minimum of four clocks due to a handshake with the current symmetric owner.

  • Page 67: Request Stall States

    BUS PROTOCOL 4.1.3.2.1. Request Stall States The request stall protocol can be described using three states: The “free” state in which transac- tions can be driven to the bus normally, one every 3 clocks, the “stalled” state in which no trans- actions are driven to the bus, and the “throttled”...

  • Page 68: Figure 4-2. Symmetric Arbitration Of A Single Agent After Reset

    BUS PROTOCOL AAAA AAAA AAAA AAAA AAAA AAAA AAAA BREQ0# AAAA AAAA AAAA AAAA AAAA BREQ1# AAAA AAAA AAAA AAAA BREQ2# AAAA AAAA AAAA AAAA AAAA BREQ3# AAAA AAAA AAAA AAAA BPRI# AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA RESET#...

  • Page 69: Signal Deassertion After Bus Reset

    BUS PROTOCOL 4.1.4.2. SIGNAL DEASSERTION AFTER BUS RESET Figure 4-3 illustrates how signals are deasserted after a bus reset. This relaxed deassertion pro- tocol gives all bus agents time to initialize. Since agents must deassert bus signals in response to both BINIT# and RESET#, agents will respond to both reset assertions in the same fashion.

  • Page 70: Delay Of Transaction Generation After Reset

    BUS PROTOCOL 4.1.4.3. DELAY OF TRANSACTION GENERATION AFTER RESET Figure 4-4 illustrates how transactions can be prevented from being issued to the bus after reset in order to give all bus agents time to initialize. Note that symmetric arbitration is not affected by the state of BNR#.

  • Page 71: Symmetric Arbitration With No Lock

    BUS PROTOCOL 4.1.4.4. SYMMETRIC ARBITRATION WITH NO LOCK# Figure 4-5 illustrates arbitration between two or more symmetric agents while LOCK# and BPRI# stay inactive. Because LOCK# and BPRI# remain inactive, bus ownership is determined based on a Rotating ID and bus ownership state. The symmetric agent that wins the bus releases it to the other agent as soon as possible (the Pentium Pro processor limits it to one transaction, unless the outstanding operation is locked).

  • Page 72: Symmetric Bus Arbitration With No Transaction Generation

    BUS PROTOCOL Since BPRI# is observed inactive in T3 and the bus is not stalled, in T4, agent 0 can begin a new Request Phase. (If BPRI# has been asserted in T3, the arbitration event, the updating of the Ro- tating ID, and ownership states would not have been affected.

  • Page 73: Bus Exchange Among Symmetric And Priority Agents With No Lock

    BUS PROTOCOL BREQ0# BREQ1# BREQ2# BREQ3# BPRI# BNR# ADS# AAAAAA AAAAA AAAAAA A A AA A A AA AAAAAA AA A AAAA AAAAAAAAAAAAAAAA {REQUEST} {rotating id} Figure 4-6. Symmetric Arbitration with no Transaction Generation This figure is the same as Figure 4-5 up until T9. In T9, the clock that bus agent 2 wins bus ownership, bus agent 2 deasserts BREQ2# because the need to drive the transaction was removed (for example, on the Pentium Pro processor, if a transaction is pending to writeback a replaced cache line and it gets snooped, HITM# will be...

  • Page 74: Figure 4-7. Bus Exchange Among Symmetric And Priority Agent With No Lock

    BUS PROTOCOL BREQ0# BREQ1# BREQ2# BREQ3# BPRI# LOCK# I/O a I/O b ADS# AAAA AA AA AAAA AA AA AA AA AAAA AA AA AA AA AAAA AAAA AA AA A A AA AA AAAA AA AA AAAA AAAA A A AA AA AAAA AA AA AAAA AAAA...

  • Page 75: Symmetric And Priority Bus Exchange During Lock

    BUS PROTOCOL 4.1.4.7. SYMMETRIC AND PRIORITY BUS EXCHANGE DURING LOCK# Figure 4-8 illustrates an ownership request made by both a symmetric and a priority agent during an ongoing indivisible sequence by a symmetric owner. When this is the case, LOCK# takes pri- ority over BPRI#.

  • Page 76: Bnr# Sampling

    BUS PROTOCOL Since agent 1 observed active BPRI# in T12, it guarantees no new request generation beginning T13. In T13, the priority agent deasserts BPRI#. In T15, three clocks from the previous request and at least two clocks from BPRI# deassertion agent 1, the current symmetric owner issues request 1a.

  • Page 77: Figure 4-10. Bnr# Sampling After Ads

    BUS PROTOCOL In T14, BNR# is again sampled asserted, so the state transitions to stalled in T15 and no further transactions are issued. In T16, BNR# is sampled deasserted, which causes the state machine to transition to throttled in T17. In T18, BNR is again sampled deasserted, which transitions the state machine to free in T19.

  • Page 78: Symmetric Agent Arbitration Protocol Rules

    BUS PROTOCOL 4.1.5. Symmetric Agent Arbitration Protocol Rules 4.1.5.1. RESET CONDITIONS On observation of active RESET# or BINIT#, all BREQ[3:0]# signals must be deasserted in one or two clocks. On observation of active AERR# (with AERR# observation enabled), all BREQ[3:0]# signals must be deasserted in the next clock. All agents also re-initialize Rotating ID to three and ownership state to idle.

  • Page 79: Ownership From Busy State

    BUS PROTOCOL 4.1.5.4. OWNERSHIP FROM BUSY STATE When the ownership state is busy, the next arbitration event begins with the deassertion of BREQn# by the current symmetric owner. 4.1.5.4.1. Bus Parking and Release with a Single Bus Request When the ownership state is busy, bus parking is an accepted mode of operation. The symmetric owner can retain ownership even if it has no pending requests, provided no other symmetric agent has an active arbitration request.

  • Page 80: Bus Request Assertion

    BUS PROTOCOL 4.1.6.2. BUS REQUEST ASSERTION The priority agent can activate BPRI# to seek bus ownership provided the reset conditions de- scribed in Section 4.1.6.1., “Reset Conditions” are satisfied. BPRI# can be deactivated at any time. On observing active BPRI#, all symmetric agents guarantee no new non-locked requests are generated.

  • Page 81: Bus Signals

    BUS PROTOCOL 4.2.1. Bus Signals The Request Phase bus signals are ADS#, A[35:3]#, REQa[4:0]#, REQb[4:0]#, ATTR[7:0]#, DID[7:0]#, BE[7:0]#, EXF[4:0]#, AP[1:0]#, and RP#. In addition, the LOCK# signal is driven during this phase. Request Phase signals are bused among all agents. Since information is car- ried during two clocks, the first clock is identified with the suffix a and the second clock is iden- tified with the suffix b.

  • Page 82: Request Phase Protocol Rules

    BUS PROTOCOL In T6, agent 0 issues another transaction, and in T8, the internal state is updated appropriately. In the series of clocks indicated in the diagram by T10, five more transactions become outstand- ing (this status is indicated by the {rcnt}). In T13, the 8th transaction is issued as indicated on the bus by ADS# assertion in T13.

  • Page 83: Bus Signals

    BUS PROTOCOL during Error Phase, then all agents remove the transaction from their In-order Queue, cancel subsequent transaction phases, remove bus requests, and reset their bus arbiters. Reset of the bus arbiters enables errors in the Arbitration Phase to be corrected. The transaction may be retried. 4.3.1.

  • Page 84: Snoop Phase Protocol Description

    BUS PROTOCOL The CLEAN result means that at the end of the transaction, no other caching agent will retain the addressed line in its cache, and that the requesting agent can store the cache line in any state (Modified, Exclusive, Shared or Invalid). The MODIFIED result means that the addressed line is in the modified state in an agent on the Pentium Pro processor bus.

  • Page 85: Stalled Snoop Phase

    BUS PROTOCOL In T1, there are no transactions outstanding on the bus and {scnt} is 0. In T2, transaction 1 is issued. In T4, as a result of the transaction driven in T2, {scnt} is incremented. In T5, transaction 2 is issued. In T6, which is four clocks after the corresponding ADS# in T2, the snoop results for transaction 1 are driven.

  • Page 86: Snoop Phase Protocol Rules

    BUS PROTOCOL Phase is extended, {scnt} is not decremented. Because the Snoop Phase is extended, the value of DEFER# is a “don’t care”. On observing active HIT# and HITM# in T7, all agents determine that the transaction’s Snoop Phase is extended by two additional clocks through T8. In T8, the slower snooping agent is ready with valid snoop results and needs no additional Snoop Phase extensions.

  • Page 87: Valid Snoop Phase

    BUS PROTOCOL For all transactions with LOCK# inactive, HITM# active guarantees in-order completion. Dur- ing unlocked transactions, HITM# overrides the assertion of DEFER#. If DEFER# is asserted during the Snoop Phase of a locked operation, the locked operation is pre- maturely aborted.

  • Page 88: Bus Signals

    BUS PROTOCOL 4.5.1.1. BUS SIGNALS The Response Phase signals are TRDY#, RS[2:0]#, and RSP#. These signals are bused. RSP# provides parity support only for RS[2:0]#. The transaction response is encoded on the RS[2:0]# signals. TRDY# is only asserted for transactions with write or writeback data to transfer. The response encodings are indicated in Table 4-2.

  • Page 89: Figure 4-14. Rs[2:0]# Activation With No Trdy

    BUS PROTOCOL ADS# REQ0# HITM# TRDY# RS[2:0]# DBSY# {rcnt} Figure 4-14. RS[2:0]# Activation with no TRDY# Three transactions are issued in clocks T1, T4, and T7. None of these transactions have write data to transfer as indicated by the REQa0# signal. The Snoop Phase for each transaction indicates that no implicit writeback data will be trans- ferred and the response agent indicated by the address will provide the transaction response and the read data if there is any.

  • Page 90: Write Data Transaction Response

    BUS PROTOCOL 4.5.2.2. WRITE DATA TRANSACTION RESPONSE Figure 4-15 shows a transaction with a simple request initiated data transfer. A request initiated data transfer means that the request agent issuing the transaction has write data to transfer. Note that TRDY# is always asserted after the response for transaction n-1 is driven and before the transaction response for transaction n is driven.

  • Page 91: Implicit Writeback On A Read Transaction

    BUS PROTOCOL 4.5.2.3. IMPLICIT WRITEBACK ON A READ TRANSACTION Figure 4-16 shows a read transaction with an implicit writeback. TRDY# is asserted in this op- eration because there is writeback data to transfer. Note that the implicit writeback response must be asserted exactly one clock after valid TRDY# assertion is sampled. That is, TRDY# is sampled active and DBSY# is sampled inactive.

  • Page 92: Implicit Writeback With A Write Transaction

    BUS PROTOCOL 4.5.2.4. IMPLICIT WRITEBACK WITH A WRITE TRANSACTION Figure 4-17 shows a write transaction combined with a hit to a modified line that requires an im- plicit writeback. This operation has two data transfers and requires two assertions of TRDY#. The first TRDY# is asserted by the receiver of the write data whenever it is ready to receive the write data.

  • Page 93: Response Phase Protocol Rules

    BUS PROTOCOL 4.5.3. Response Phase Protocol Rules 4.5.3.1. REQUEST INITIATED TRDY# ASSERTION A request initiated transaction is a transaction where the request agent has write data to transfer. The addressed agent asserts TRDY# to indicate its ability to receive data from the request agent intending to perform a write data operation.

  • Page 94: Rs[2:0]# Encoding

    BUS PROTOCOL 4.5.3.4. RS[2:0]# ENCODING Valid response encodings are determined based on the snoop results and the following request: Hard Failure is a valid response for all transactions and indicates transaction failure. The • requesting agent is required to take recovery action. Implicit Writeback is a required response when HITM# is asserted during the Snoop •...

  • Page 95: Data Phase

    BUS PROTOCOL A response that does not require the data bus (no data response, deferred response, retry • response, or hard failure response) may be driven even if DBSY# is active due to a previous transaction. On observation of active RS[2:0]# response, the Transaction Queues are updated and {rcnt} is decremented.

  • Page 96: Simple Read Transaction

    BUS PROTOCOL ADS# REQa0# HITM# TRDY# DBSY# AAAAAA A AAAAAA AAAAAA AAAAAA A AAAAAA AA AAAA AA A AAAA AAAAAA AA AAAAAA D[63:0]# DRDY# RS[[2:0]# Figure 4-18. Request Initiated Data Transfer The write transaction is driven in T1 as indicated by active ADS# and REQa0#. TRDY# is driven 3 clocks later in T4.

  • Page 97: Implicit Writeback

    BUS PROTOCOL ADS# REQa0# HITM# TRDY# DBSY# AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA A AAAAAA A A AA AA A AAAA AAAAAA D[63:0]# DRDY# RS[2:0]# Figure 4-19. Response Initiated Data Transfer A read transaction is driven in T1 as indicated by the ADS# and REQa0# pins. Because the trans- action is a read and HITM# indicates that there will be no implicit writeback data, TRDY# is not asserted for this transaction.

  • Page 98: Full Speed Read Partial Transactions

    BUS PROTOCOL ADS# REQa0# HITM# TRDY# DBSY# AAAAAA A AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AA AAAAAA AAAAAA A A AAA A AA AAAA A AA AAAA AA A AAAA A A AA A A AAA A AA AAAA D[63:0]# DRDY# RS[2:0]# Figure 4-20.

  • Page 99: Relaxed Dbsy# Deassertion

    BUS PROTOCOL ADS# A A AA AAAA A A AA AAAA A A AA AA A AAAA A A AA AA A A A AA AAA A A A AA {REQUEST} HITM# TRDY# DBSY# AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA A AAAAAA A A AA...

  • Page 100: Full Speed Read Line Transfers (Same Agent)

    BUS PROTOCOL ADS# A A AAA A A AAA A A AAA A AA AAA A A A AAA AAAA A AA A AA AAAA A A A AA {REQUEST} HITM# TRDY# DBSY# AAAAAA A AAAAAA AAAAAA AAAAAA A AAAAAA A AAAAAA AA AAAA AA AAAAAAAAAAAAAAAAAAAA...

  • Page 101: Full Speed Write Partial Transactions

    BUS PROTOCOL ADS# A A AA AAAA A A AA AAAA A A AA AAA A A A AA AAA A A A AA AAA A A A AA {REQUEST} HIT# TRDY# DBSY# AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA A AAAAAA A A AA D[63:0]#...

  • Page 102: Full Speed Write Line Transactions (Same Agents)

    BUS PROTOCOL ADS# A A AAA A A AAA A A AAA A A AAA A AA A A AAA A AA AAAA A A A AAA {REQUEST} HIT# TRDY# DBSY# AAAAAA A AAAAAA AAAAAA AAAAAA A AAAAAA A A AA AAAAAA A AAAAAA AAAAAA...

  • Page 103: Figure 4-25. Full Speed Write Line Transactions

    BUS PROTOCOL ADS# A A AA AAAA A A AA AAAA A A AA AA A AAAA A A AA AA A A A AA AAA A A A AA {REQUEST} HIT# TRDY# DBSY# AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA AAAAAA A A AA...

  • Page 104: Data Phase Protocol Rules

    BUS PROTOCOL 4.6.3. Data Phase Protocol Rules 4.6.3.1. VALID DATA TRANSFER All Data Phase bus signals; DBSY#, DRDY#, D[63:0]#, and DEP[7:0]# are driven by the agent responsible for data transfer. Multi-clock data transfers begin with assertion of DBSY# and com- plete with deassertion of DBSY# no sooner than one clock prior to the last data transfer.

  • Page 105: Bus Transactions And Operations

    Bus Transactions and Operations...

  • Page 106: Bus Transactions Supported

    CHAPTER 5 BUS TRANSACTIONS AND OPERATIONS This chapter describes in detail the bus transactions and operations supported by the Pentium Pro processor bus. 5.1. BUS TRANSACTIONS SUPPORTED Figure 5-1 lists the different bus transactions. All Bus Transactions Memory Other Read data: Mem Read I/O Read Interrupt Acknowledge...

  • Page 107: Bus Transaction Description

    BUS TRANSACTIONS AND OPERATIONS The transactions classified as deferred transactions may or may not send data in normal opera- tion. It will return what is expected from the original transaction, unless the Snoop Result Phase indicates that data will return when not expected (HITM#). The transactions classified as no data transactions require no data transfer.
  • Page 108 BUS TRANSACTIONS AND OPERATIONS Ab[15:3]# are used to encode additional information about the transaction as follows: Ab[15:8]# Ab[7:3]# BE[7:0]# SMMEM# SPLCK# rsvd DEN# rsvd The ASZ[1:0]# signals are used to support agents with different memory addressing capability to coexist on the same bus. The bits indicate what address range is being addressed as shown in the table below.
  • Page 109 BUS TRANSACTIONS AND OPERATIONS For write transactions, TRDY# assertion is required, even when no request-initiated data is being transferred. This simplifies this rare special case (Pentium Pro processor will not issue this transaction). The request agent must not assert DRDY# in response to TRDY#. SMMEM# is asserted while the requestor is in System Management Mode (see Section 5.2.3.6.7., “SMI Acknowledge”).

  • Page 110: Memory Read Transactions

    BUS TRANSACTIONS AND OPERATIONS 5.2.1.1. MEMORY READ TRANSACTIONS REQa[2:0]# code read D/C#=0 data read D/C#=1 Memory Read Transactions perform reads of memory or memory-mapped I/O. REQa[1]# indi- cates whether the read is for code or data. This can be used to make cache coherency assump- tions (see Chapter 7, Cache Protocol).

  • Page 111: Reserved Memory Write Transaction

    ® Pro processor is backwards compatible with previous implementations of the Intel Architecture I/O T h e P en ti u m space. A[16]# is active whenever an I/O access is made to 4 bytes from addresses 0FFFDH, 0FFFEH, or 0FFFFH.

  • Page 112: Request Initiator Responsibilities

    BUS TRANSACTIONS AND OPERATIONS LEN[1:0]# Transaction Length 0 - 8 bytes 16 bytes 32 bytes Reserved BE[7:0]# is used in conjunction with LEN[1:0]#. If 8 bytes or more are to be transferred, then BE[7:0]# indicates that all bytes are enabled. If less than 8 bytes are to be transferred, then BE[7:0]# indicates which bytes.

  • Page 113: Request Initiator Responsibilities

    BUS TRANSACTIONS AND OPERATIONS REQa[4:0]# REQb[4:0]# read W/R#=0 write W/R#=1 DSZ[1:0]# rsvd Ab[15:8]# Ab[7:3]# SMMEM# SPLCK#=0 rsvd DEN# rsvd These transactions drive REQa[0]#active if request initiated data is being sent. The Central Agent will then drive TRDY#. 5.2.3.1. REQUEST INITIATOR RESPONSIBILITIES Generate the request with valid encodings.

  • Page 114: Branch Trace Message

    BUS TRANSACTIONS AND OPERATIONS 5.2.3.5. BRANCH TRACE MESSAGE Branch Trace Messages produce 64 bits of data. If execution tracing is enabled, an agent issues a Branch Trace Message transaction for branches taken. The address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# contain the linear address of the target. D[31:0]# contain either the address of the first byte of the branch instruction or the address of the instruction im- mediately following the branch.

  • Page 115: Shutdown

    BUS TRANSACTIONS AND OPERATIONS 5.2.3.6.1. Shutdown An agent issues a Shutdown Transaction to indicate that it has detected a severe software error that prevents further processing. The Pentium Pro processor issues a Shutdown Transaction if any other exception occurs while the processor is attempting to call the double fault handler. The internal caches remain in the same state unless a snoop hits a modified line.

  • Page 116: Sync

    BUS TRANSACTIONS AND OPERATIONS Event Immediate Action Final State INTR Interrupt Handler Entry Do not return to Halt on IRET NMI Handler Entry Do not return to Halt on IRET INIT# Reset Handler Do not return to Halt RESET# Reset Handler Do not return to Halt STPCLK# STPCLK Acknowledge...

  • Page 117: Deferred Reply Transaction

    BUS TRANSACTIONS AND OPERATIONS The SMI Acknowledge Transaction can be observed by the bridge agents to determine when an agent enters or exits SMM mode. 5.2.4. Deferred Reply Transaction An agent issues a Deferred Reply Transaction to complete an earlier transaction for which the response was deferred.

  • Page 118: Addressed Agent Responsibilities (Original Requestor)

    BUS TRANSACTIONS AND OPERATIONS Phase of the Deferred Reply (the Snoop Result Phase indicates all changes in the length of data returned). The deferring agent may assert DEFER# in the Snoop Result Phase of the Deferred Reply to retry the original transaction. A Deferred Reply may receive any response except a Deferred Response.

  • Page 119: Memory Agent Responsibilities

    BUS TRANSACTIONS AND OPERATIONS an implicit writeback. The response for a transaction that contains an implicit writeback is the Implicit Writeback response. 5.3.1.1. MEMORY AGENT RESPONSIBILITIES On observing HITM# active in the Snoop Phase, the addressed memory agent remains the re- sponse agent but changes its response to an implicit writeback response.

  • Page 120: Transferring Snoop Responsibility

    BUS TRANSACTIONS AND OPERATIONS 5.3.2. Transferring Snoop Responsibility A requesting agent picks up snoop responsibility for the cache line after observing a transac- tion’s Snoop Phase. When a requesting agent accepts snoop responsibility for a cache line and immediately drops that responsibility in response to a subsequent transaction, it is allowed to use the cache line exactly once for internal use, before performing an implicit writeback.

  • Page 121: Deferred Operations

    BUS TRANSACTIONS AND OPERATIONS In T5, P1 observes request 2 and notes that the request is to the same cache line for which it is expecting ownership in T6. In T6, P1 observes inactive DEFER# and confirms that the transac- tion has been committed for in-order completion.

  • Page 122: Response Agent Responsibilities

    BUS TRANSACTIONS AND OPERATIONS For every transaction, only one agent is allowed to assert DEFER#. Normally it is the responsi- bility of the agent addressed by the transaction. When the addressed agent always guarantees in- order completion, the responsibility can be given to a unique third party agent who can assert DEFER# on behalf of the addressed agent.

  • Page 123: Requesting Agent Responsibilities

    BUS TRANSACTIONS AND OPERATIONS available during the request phase of the transaction. After the transaction’s Response Phase has been driven, it must become a request bus owner and initiate a Deferred Reply Transaction using the Deferred ID as the address. It must also reclaim free queue entries in the deferred reply pool. 5.3.3.2.

  • Page 124: Locked Operations

    BUS TRANSACTIONS AND OPERATIONS Before T9, the addressed response agent obtains the data required in the original request. In T9, the original response agent issues a Deferred Reply Transaction, using the value latched from the DID[7:0]# signals in the original transaction as the address. In T13, the response agent drives a valid level on the HIT# signal to indicate the final cache state of the returned line.

  • Page 125: Split] Bus Lock

    BUS TRANSACTIONS AND OPERATIONS 5.3.4.1. [SPLIT] BUS LOCK All variables that cannot be cache locked are locked using the standard [split] bus lock operation. A Pentium Pro processor [split] bus locked operation (read-modify-write or RMW) involves 1 or 2 memory read transactions followed by 1 or 2 memory write transactions to the same ad- dress.

  • Page 126: Range Registers

    Range Registers...

  • Page 127: Introduction

    The Pentium Pro processor Memory Type Range Registers (MTRRs) are model specific regis- ters specifying the types of memory occupying different physical address ranges. Some of this information was available to previous Intel processors via external bus signals (for example, KEN# and WB/WT#).
  • Page 128 RANGE REGISTERS writethrough. The memory types are defined for specific address ranges based on range regis- ters. The memory types currently defined, are shown in Table 6-1. The Pentium Pro processor drives the memory type to the Pentium Pro processor bus in the second clock of the Request Phase on the ATTR[3:0]# (attribute) pins.

  • Page 129: Memory Type Descriptions

    RANGE REGISTERS 6.3. MEMORY TYPE DESCRIPTIONS This section provides detailed descriptions of the Pentium Pro processor’s memory types: UC, WC, WT, WP, and WB. 6.3.1. UC Memory Type The UC (uncacheable) memory type provides an uncacheable memory space. The processor’s accesses to UC memory are executed in program order, without reordering.

  • Page 130: Wp Memory Type

    RANGE REGISTERS 6.3.4. WP Memory Type The WP (write-protected) memory type is used for cacheable memory for which reads can hit the cache and read misses cause cache fills, while writes bypass the cache entirely. WP memory can be viewed as a combination of WT memory for reads and UC (nonexistent) memory for writes.

  • Page 131: Cache Protocol

    Cache Protocol...

  • Page 132: Line States

    CHAPTER 7 CACHE PROTOCOL The Pentium Pro processor and Pentium Pro processor bus support a high performance cache hierarchy with complete support for cache coherency. The cache protocol supports multiple caching agents (processors) executing concurrently, writeback caching, and multiple levels of cache.

  • Page 133: Memory Types, And Transactions

    CACHE PROTOCOL — E (Exclusive) The line is in this cache, contains the same value as in memory, and is Invalid in all other caches. Internally reading the line causes no bus activity. Internally writing the line causes no bus activity, but changes the line’s state to Modified. —...

  • Page 134: Naming Convention For Transactions

    CACHE PROTOCOL BRP (Bus Read Part-line). A Bus Read Part-line transaction indicates that a requesting agent issued a Memory Read Transaction for less than a full cache line. BLR (Bus Locked Read). A Bus Locked Read transaction indicates that a requesting agent is- sued a bus locked Memory Read Transaction.

  • Page 135: Data Integrity

    Data Integrity...
  • Page 136 CHAPTER 8 DATA INTEGRITY The chapter has been updated from the EBS 3.0 to simplify and clarify the Data Integrity features of the Pentium Pro processor bus, as well as updating the Pentium Pro processor implementation. The Pentium Pro processor and the Pentium Pro processor bus incorporate several advanced data integrity features to improve error detection, retry, and correction.

  • Page 137: Error Classification

    DATA INTEGRITY 8.1. ERROR CLASSIFICATION The Pentium Pro architecture uses the following error classification. An implementation may al- ways choose to report an error in a more severe category to simplify its logic. Recoverable error (RE): The error can be corrected by a retry or by using ECC infor- •...

  • Page 138: Table 8-1. Direct Bus Signal Protection

    DATA INTEGRITY Table 8-1. Direct Bus Signal Protection Signal Protects Phase ASZ[1:0]# ASZ[1:0]# Address range ADS#,REQ[4:0]# Request AP[0]# A[23:3]# Request AP[1]# A[31:24]# Request 0 <= Address < 4GB A[35:24]# Request 4GB <= Address < 64GB Reserved Request Reserved RSP# RS[2:0]# DEP[7:0]# D[63:0]# Data...

  • Page 139: Bus Signals Protected Indirectly

    DATA INTEGRITY 8.2.2. Bus Signals Protected Indirectly Some bus signals are not directly protected by parity or ECC. However, they can be indirectly protected due to a requirement to follow a strict protocol. Although the Pentium Pro processor implementation does not directly detect the errors, future Pentium Pro processor generations or other bus agents can enhance error detection or correction for the bus by checking for protocol violations.
  • Page 140 DATA INTEGRITY Snoop Signals, HIT#, HITM#, and DEFER#. These signals can only be asserted during • a valid snoop window. The following snoop protocol violation errors can be detected by all agents: — Activation of snoop signals outside of a valid snoop window. —...

  • Page 141: Unprotected Bus Signals

    DATA INTEGRITY Target Ready Signal, TRDY#. • — TRDY# protocol violation can be detected by all agents when TRDY# assertion is detected with response assertion or when TRDY# is deasserted in less than three clocks from the previous TRDY# deassertion, or when TRDY# is deasserted even when it is required to be stretched due to DBSY# active from the previous data transfer.

  • Page 142: Hard-Error Response

    DATA INTEGRITY Arbitration time-out. If BPRI# is asserted for more than a reasonable number of clocks, • then the central agent should indicate a bus protocol violation. 8.2.5. Hard-error Response The target can assert a hard-error response in the Response Phase to a transaction that has gen- erated an error.

  • Page 143: Ierr# Signal

    DATA INTEGRITY 8.3.3. IERR# Signal The IERR# signal is asserted by a Pentium Pro processor when an unrecoverable error is not handled with the MCA software log (MCA disabled). The IERR# signal stays asserted until deasserted by the NMI handler or RESET#/INIT# resets the processor. BERR# can be config- ured to report IERR# assertion.

  • Page 144: Binit# Signal And Protocol

    DATA INTEGRITY 8.3.5. BINIT# Signal and Protocol BINIT# is asserted when any Pentium Pro processor agent detects a fatal error and BINIT# driv- er is enabled. Sampling of BINIT#, if enabled, resets all bus state, clearing a path for an excep- tion handler (disabling of BINIT# driving/sampling is provided for power on diagnostics only).

  • Page 145: Figure 8-2. Binit# Protocol Mechanism

    DATA INTEGRITY Processor 0 Processor 0 BINIT# BINIT# Processor 1 Processor 1 BINIT# BINIT# Processor 2 Processor 2 BINIT# BINIT# Processor 3 Processor 3 BINIT# BINIT# BINIT# BINIT# Processor 0 observes BINIT# active in CLK 2 Processor 0 observes BINIT# inactive in CLK 2 and asserts BINIT# for exactly three clocks.

  • Page 146: Speculative Errors

    DATA INTEGRITY Bus Read 1-bit ECC Recoverable Bus Request 1st AERR# L2 1-bit ECC Error Speculative Bus Read 2-bit ECC Bus Request 2nd AERR# Non- Bus Hard Error Response CR4.MCE L2 2-bit ECC recoverable !Checker Internal Parity !MCIP Master Error FRCERR ELSE Checker...

  • Page 147: Pentium Pro Processor Time-Out Counter

    DATA INTEGRITY ® 8.4.3. Pentium Pro Processor Time-Out Counter The Pentium Pro processor implements a time-out counter, which issues a fatal error if the pro- cessor is stalled for a long period of time. This mechanism is not related to the Pentium Pro pro- cessor bus time-out errors described in Section 8.2.4., “Time-out Errors”.

  • Page 148: Configuration

    Configuration...

  • Page 149: Description

    CHAPTER 9 CONFIGURATION This chapter describes configuration options for Pentium Pro processors and the Pentium Pro processor bus agents. A system can contain multiple Pentium Pro processors. Processors can be used in a multipro- cessor configuration, with one to four Pentium Pro processors on a single Pentium Pro processor bus.

  • Page 150: Output Tristate

    CONFIGURATION Pentium Pro processor bus agents can also be configured with some additional software config- uration options. These options can be changed by writing to a power-on configuration register which all bus agents must implement. These options should be changed only after taking into account synchronization between multiple Pentium Pro processor bus agents.

  • Page 151: Built-In Self Test

    CONFIGURATION 9.1.2. Built-in Self Test The Pentium Pro processor executes its built-in self test (BIST) if the INIT# signal is sampled active on the RESET# signal’s active-to-inactive transition. In an MP cluster based on the system architecture, the INIT# pin of different processors may or may not be bused. No software control is available to perform this function.

  • Page 152: Berr# Driving Policy For Target Bus Errors

    CONFIGURATION 9.1.8. BERR# Driving Policy for Target Bus Errors A Pentium Pro processor bus agent can be enabled to drive the BERR# signal if the addressed (target) bus agent detects an error. After active RESET#, BERR# signal driving is disabled on target bus errors.

  • Page 153: 9.1.14. Power-On Reset Vector

    CONFIGURATION 9.1.14. Power-on Reset Vector The reset vector on which the Pentium Pro processor begins execution after an active RESET# is controlled by sampling A6# on the RESET# signal’s active-to-inactive transition. The reset vector for the Pentium Pro processor is 0FFFF0H (1Meg - 16) if A6# is sampled active. Other- wise, the reset vector is 0FFFFFFF0H (4Gig - 16).

  • Page 154: 9.1.18. Symmetric Agent Arbitration Id

    CONFIGURATION 9.1.18. Symmetric Agent Arbitration ID The Pentium Pro processor bus supports symmetric distributed arbitration among one to four agents. Each Pentium Pro processor identifies its initial position in the arbitration priority queue based on an agent ID supplied at configuration. The agent ID can be 0, 1, 2, or 3. Each logical Pentium Pro processor (not a FRC master/checker pair) on a particular Pentium Pro processor bus must have a distinct agent ID.

  • Page 155: Figure 9-2. Br[3:0]# Physical Interconnection

    CONFIGURATION Priority Agent BPRI# Agent 2 Agent 3 Agent 0 Agent 1 BREQ0# BREQ1# BREQ2# System Interface Logic BREQ3# During Reset Figure 9-2. BR[3:0]# Physical Interconnection At the RESET# signal’s active-to-inactive transition, system interface logic is responsible for as- sertion of the BREQ0# bus signal. BREQ[3:1]# bus signals remain deasserted. All Pentium Pro processors sample their BR[3:1]# pins on the RESET signal’s active-to-inactive transition and determine their agent ID from the sampled value.

  • Page 156: 9.1.19. Low Power Standby Enable

    CONFIGURATION If FRC is used, then two physical processors are combined to create a single logical processor. Processors with agent ID 0 and 2 are designated as FRC-masters and use their agent ID as their parallel bus arbitration ID. Processors with agent ID 1 and 3 are designated as FRC checkers for processors 0 and 2 respectively and assume the characteristics of their respective masters as shown in Table 9-3.

  • Page 157: Clock Frequencies And Ratios

    CPUs at different core frequencies by supplying a different ratio to individual CPU pins. Intel may also introduce different bus frequency to core frequency ratios than the ones currently specified. In order to introduce ratios other than 2, 3, and 4,...

  • Page 158: Clock Frequencies And Ratios At Product Introduction

    CONFIGURATION 9.2.1. Clock Frequencies and Ratios at Product Introduction Only the 2X ratio is supported by the Pentium Pro 133 MHz processor. All other combinations are reserved. 9.3. SOFTWARE-PROGRAMMABLE OPTIONS All bus agents are required to maintain some software read/writable bits in the power-on config- uration register for software-configured options.
  • Page 159 CONFIGURATION ® Table 9-5. Pentium Pro Processor Power-on Configuration Register (Contd.) Pentium ® Processor Pentium Pro Active Processor Feature Signals Register Bits Read/Write Default 1 Mbyte power-on reset vector D14=1 Read N.A. FRC Mode enabled D15=1 Read N.A. APIC cluster ID A12#,A11# D17,D16 Read...

  • Page 160: Table 9-8. Pentium ® Pro Processor Power-On Configuration Register Arbitration Id Configuration

    CONFIGURATION ® Table 9-8. Pentium Pro Processor Power-on Configuration Register Arbitration ID Configuration Arb id D[21:20] 9-12...

  • Page 161: Pentium ® Pro Processor Test Access Port (Tap)

    ® Pentium Processor Test Access Port (TAP)

  • Page 162: Figure 10-1. Simplified Block Diagram Of Pentium

    CHAPTER 10 ® PENTIUM PRO PROCESSOR TEST ACCESS PORT (TAP) This chapter describes the implementation of the Pentium Pro processor test access port (TAP) logic. The Pentium Pro processor TAP complies with the IEEE 1149.1 (“JTAG”) test architec- ture standard. Basic functionality of the 1149.1-compatible test logic is described here, but this chapter does not describe the IEEE 1149.1 standard in detail.

  • Page 163: Interface

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) 10.1. INTERFACE The TAP logic is accessed serially through 5 dedicated pins on the Pentium Pro processor package: TCK: The TAP clock signal • TMS: “Test mode select,” which controls the TAP finite state machine •...
  • Page 164 PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) The following is a brief description of each of the states of the TAP controller state machine. Refer to the IEEE 1149.1 standard for detailed descriptions of the states and their operation. Test-Logic-Reset: In this state, the test logic is disabled so that normal operation of the •...

  • Page 165: 10.2.1. Accessing The Instruction Register

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) Exit2-DR: This is a temporary state. All registers retain their previous values. • Update-DR: Data from the shift register path is loaded into the latched parallel outputs of • the selected Data Register (if applicable) on the falling edge of TCK. This (and Test-Logic- Reset) is the only state in which the latched paralleled outputs of a data register can change.

  • Page 166: Figure 10-4. Operation Of The Pentium

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) (a) Capture-IR (b) Shift-IR (c) Update-IR AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AAAA AAAA AAAA AAAA AAAA...

  • Page 167: 10.2.2. Accessing The Data Registers

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) controller state Instruc- “IDCODE” “BYPASS tion Figure 10-5. TAP Instruction Register Access 10.2.2. Accessing the Data Registers The test data registers in the Pentium Pro processor are designed in the same way as the instruc- tion register, with components (i.e.

  • Page 168: Table 10-1. 1149.1 Instructions In The Pentium

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) TAP instructions in the Pentium Pro processor are 6 bits long. For each listed instruction, the table shows the instruction’s encoding, what happens on the Pentium Pro processor pins, which TAP data register is selected by the instruction, and the actions which occur in the selected data register in each of the controller states.

  • Page 169: Data Register Summary

    Contains the Pentium Pro processor device identification code in the format shown in Table 10-3. The manufacturer’s identification code is unique to Intel. The part number code is divided into four fields: VCC (3.3v supply), product type (an Intel Architecture compatible processor), generation (sixth generation), and model (first in the Pentium Pro processor family).

  • Page 170: 10.4.3. Bist Result Boundary Scan Register

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) Table 10-3. Device ID Register Part Number Product Manufacturing Type Generation Model Version “1” Entire Code Size xxxx 000001 0110 00001 00000001001 xxxx100000101100 Binary 0001000000010011 x82c1013 10.4.3. BIST Result Boundary Scan Register Holds the results of BIST. It is loaded with a logical 0 on successful BIST completion. 10.4.4.

  • Page 171: Table 10-4. Tap Reset Actions

    PENTIUM® PRO PROCESSOR TEST ACCESS PORT (TAP) Table 10-4. TAP Reset Actions TAP logic affected TAP reset state action Related TAP instructions Instruction Register Loaded with IDCODE op-code Pentium ® Pro processor boundary disabled CLAMP, HIGHZ, EXTEST scan logic Pentium Pro processor TDO pin tri-stated The TAP can be transitioned to the Test-Logic-Reset state in any one of three ways: Power on the Pentium Pro processor.

  • Page 172: Electrical Specifications

    Electrical Specifications...

  • Page 173: The Pentium Pro Processor Bus And Vref

    Pentium Pro processor bus including trace lengths is highly recommended when designing a system with a heavily loaded GTL+ bus. See Intel’s technical documents on the world wide web page (http:\\www.intel.com) to down-load the buffer models for the Pentium Pro processor in IBIS format.

  • Page 174: Power Management: Stop Grant And Auto Halt

    ELECTRICAL SPECIFICATIONS 11.2. POWER MANAGEMENT: STOP GRANT AND AUTO HALT The Pentium Pro processor allows the use of Stop Grant and Auto HALT modes to immediately reduce the power consumed by the device. When enabled, these cause the clock to be stopped to most of the CPU’s internal units and thus significantly reduces power consumption by the CPU as a whole.

  • Page 175: Decoupling Recommendations

    ELECTRICAL SPECIFICATIONS 28 V cc S inputs (3.3V) are for use by the on-package L2 Cache die of some processors. One V cc 5 pin is provided for use by the fan of the OverDrive processor. V cc 5, V cc S and V cc P must remain electrically separated from each other.

  • Page 176: Vccs Decoupling

    ELECTRICAL SPECIFICATIONS Adequate decoupling capacitance should be placed near the power pins of the Pentium Pro pro- cessor. Low inductance capacitors such as the 1206 package surface mount capacitors are rec- ommended for the best high frequency electrical performance. Forty (40) 1µF 1206-style capacitors with a ±22% tolerance make a good starting point for simulations as this is our rec- ommended decoupling when using a standard Pentium Pro processor Voltage Regulator Mod- ule.

  • Page 177: Bclk Clock Input Guidelines

    ELECTRICAL SPECIFICATIONS 11.5. BCLK CLOCK INPUT GUIDELINES The BCLK input directly controls the operating speed of the GTL+ bus interface. All GTL+ ex- ternal timing parameters are specified with respect to the rising edge of the BCLK input. Clock multiplying within the processor is provided by an internal Phase Lock Loop (PLL) which re- quires a constant frequency BCLK input.

  • Page 178: Figure 11-4. Example Schematic For Clock Ratio Pin Sharing

    ELECTRICAL SPECIFICATIONS Using CRESET# (CMOS reset), the circuit in Figure 11-4 can be used to share the pins. The pins of the processors are bussed together to allow any one of them to be the compatibility processor. The component used as the multiplexer must not be powered by more than 3.3V in order to meet the Pentium Pro processor’s 3.3V tolerant buffer specifications.

  • Page 179: 11.5.2. Mixing Processors Of Different Frequencies

    Mixing components of different internal clock frequencies is not supported and has not been val- idated by Intel. One should also note when attempting to mix processors rated at different fre- quencies in a multi-processor system that a common bus clock frequency and a set of multipliers must be found that is acceptable to all processors in the system.

  • Page 180: Jtag Connection

    ELECTRICAL SPECIFICATIONS Support for a wider range of VID settings will benefit the system in meeting the power require- ments of future Pentium Pro processors. Note that the ‘1111’ (or all opens) ID can be used to detect the absence of a processor in a given socket as long as the power supply used does not affect these lines.

  • Page 181: Signal Groups

    ELECTRICAL SPECIFICATIONS 11.8. SIGNAL GROUPS In order to simplify the following discussion, signals have been combined into groups by buffer type. All outputs are open drain and require an external hi-level source provided externally by the termination or a pull-up resistor. GTL+ input signals have differential input buffers which use V REF as their reference signal.

  • Page 182: Table 11-2. Signal Groups

    ELECTRICAL SPECIFICATIONS Table 11-2. Signal Groups Group Name Signals BPRI#, BR[3:1]# 1 , DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# GTL+ Input GTL+ Output PRDY# GTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0# 1 , D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ[4:0]#, RP# 3.3V Tolerant Input A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#,...

  • Page 183: Pwrgood

    ELECTRICAL SPECIFICATIONS 11.9. PWRGOOD PWRGOOD is a 3.3V tolerant input. It is expected that this signal will be a clean indication that clocks and the 3.3V, 5V and V cc P supplies are stable and within their specifications. Clean im- plies that the signal will remain low, (capable of sinking leakage current) without glitches, from the time that the power supplies are turned on until they come within specification.

  • Page 184: 11.11. Unused Pins

    ELECTRICAL SPECIFICATIONS 11.11. UNUSED PINS All RESERVED pins must remain unconnected. All pins named TESTHI must be pulled up, no higher than V cc P, and may be tied directly to V cc P. All pins named TESTLO pulled low and may be tied directly to V ss .

  • Page 185: Table 11-3. Absolute Maximum Ratings 1

    ELECTRICAL SPECIFICATIONS Table 11-3. Absolute Maximum Ratings 1 Symbol Parameter Unit Notes T Storage Storage Temperature °C T Bias Case Temperature under Bias °C V cc P(Abs) Primary Supply Voltage with -0.5 Operating respect to V ss Voltage + 1.4 V cc S(Abs) 3.3V Supply Voltage with respect -0.5...

  • Page 186: 11.13. D.c. Specifications

    ELECTRICAL SPECIFICATIONS 11.13. D.C. SPECIFICATIONS Table 11-4 through Table 11-7 list the D.C. specifications associated with the Pentium Pro processor. Specifications are valid only while meeting the processor specifications for case temperature, clock frequency and input voltages. Care should be taken to read all notes asso- ciated with each parameter.

  • Page 187: Table 11-5. Power Specifications 1

    ELECTRICAL SPECIFICATIONS Table 11-5. Power Specifications 1 Symbol Parameter Unit Notes P Max Thermal Design Power 23.0 29.2 @ 150MHz, 256K L2 27.5 35.0 @ 166MHz, 512K L2 24.8 31.7 @ 180MHz, 256K L2 27.3 35.0 @ 200MHz, 256K L2 32.6 37.9 @ 200MHz, 512K L2...

  • Page 188: Table 11-6. Gtl+ Signal Groups D.c. Specifications

    ELECTRICAL SPECIFICATIONS Most of the signals on the Pentium Pro processor are in the GTL+ signal group. These signals are specified to be terminated to 1.5V. The D.C. specifications for these signals are listed in Ta- ble 11-6. Care should be taken to read all notes associated with each parameter. Table 11-6.

  • Page 189: Gtl+ Bus Specifications

    ELECTRICAL SPECIFICATIONS Table 11-7. Non-GTL+ 1 Signal Groups D.C. Specifications Symbol Parameter Unit Notes V IH Input High Voltage V OL Output Low Voltage V OH Output High Voltage All Outputs are Open-Drain I OL Output Low Current µA Input Leakage Current ±...

  • Page 190: 11.15. A.c. Specifications

    ELECTRICAL SPECIFICATIONS 11.15. A.C. SPECIFICATIONS Table 11-9 through Table 11-16 list the A.C. specifications associated with the Pentium Pro pro- cessor. Timing Diagrams begin with Figure 11-7. The AC specifications are broken into catego- ries. Table 11-9 and Table 11-10 contain the clock specifications, Table 11-11 and Table 11-12 contain the GTL+ specifications, Table 11-13 contains the 3.3V tolerant Signal group specifica- tions, Table 11-14 contains timings for the reset conditions, Table 11-15 covers APIC bus tim- ing, and Table 11-16 covers Boundary Scan timing.

  • Page 191: Table 11-10. Supported Clock Ratios

    ELECTRICAL SPECIFICATIONS Table 11-10. Supported Clock Ratios PART: 5/2X 7/2X 150MHz 166MHz 180MHz 200MHz NOTE: 1. Only those indicated here are tested during the manufacturing test process. Table 11-11. GTL+ Signal Groups A.C. Specifications R L = 25Ω terminated to 1.5V, V REF = 1.0V Parameter Unit Figure...

  • Page 192: Table 11-12. Gtl+ Signal Groups Ringback Tolerance

    ELECTRICAL SPECIFICATIONS Table 11-12. GTL+ Signal Groups Ringback Tolerance Parameter Unit Figure Notes α: Overshoot 0.55 11-10 τ: Minimum Time at High 11-10 ρ: Amplitude of Ringback -100 11-10 δ: Duration of Squarewave Ringback 11-10 φ: Final Settling Voltage 11-10 NOTE: 1.

  • Page 193: Figure 11-6. 3.3V Tolerant Group Derating Curve

    ELECTRICAL SPECIFICATIONS 12.00 11.50 11.00 10.50 10.00 9.50 9.00 8.50 8.00 7.50 7.00 Figure 11-6. 3.3V Tolerant Group Derating Curve Table 11-14. Reset Conditions A.C. Specifications Parameter Unit Figure Notes T16: Reset Configuration Signals (A[14:5]#, BCLKs 11-12 Before BR0#, FLUSH#, INIT#) Setup Time deassertion of RESET# T17: Reset Configuration Signals (A[14:5]#,...

  • Page 194: Table 11-15. Apic Clock And Apic I/O A.c. Specifications

    ELECTRICAL SPECIFICATIONS Table 11-15. APIC Clock and APIC I/O A.C. Specifications Parameter Unit Figure Notes T21A: PICCLK Frequency 33.3 T21B: FRC Mode BCLK to PICCLK offset 11-11 T22: PICCLK Period 11-7 T23: PICCLK High Time 11-7 T24: PICCLK Low Time 11-7 T25: PICCLK Rise Time 11-7...

  • Page 195: Table 11-16. Boundary Scan Interface A.c. Specifications

    ELECTRICAL SPECIFICATIONS Table 11-16. Boundary Scan Interface A.C. Specifications Parameter Unit Figure Notes T30: TCK Frequency — T31: TCK Period 62.5 — 11-7 @2.0V, 1 T32: TCK High Time 11-7 @0.8V, 1 T33: TCK Low Time 11-7 (0.8V-2.0V), 1 , 2 T34: TCK Rise Time 11-7 (2.0V-0.8V), 1 , 2...

  • Page 196: Figure 11-7. Generic Clock Waveform

    ELECTRICAL SPECIFICATIONS 2.0V 1.5V 0.8V Figure 11-7. Generic Clock Waveform = Rise Time = Fall Time = High Time = Low Time = Period Figure 11-8. Valid Delay Timings = Valid Delay Tpw = Pulse Width = 1.0V for GTL+ signal group; 1.5V for 3.3V Tolerant, APIC, and JTAG signal groups V HI = GTL+ signals must achieve a DC high level of at least 1.2V.

  • Page 197: Figure 11-9. Setup And Hold Timings

    ELECTRICAL SPECIFICATIONS Figure 11-9. Setup and Hold Timings = Setup Time = Hold Time = 1.0V for GTL+ signal group; 1.5V for 3.3V Tolerant, APIC and JTAG signal groups 1.5 V Clk Ref τ α + 0.2 −ρ φ − 0.2 Clock start +0.05ns...

  • Page 198: Figure 11-11. Frc Mode Bclk To Picclk Timing

    ELECTRICAL SPECIFICATIONS Figure 11-11. FRC Mode BCLK to PICCLK Timing LAG = T21 (FRC Mode BCLK to PICCLK offset) Figure 11-12. Reset and Configuration Timings = T9 (GTL+ Input Hold Time) = T8 (GTL+ Input Setup Time) = T10 (RESET# Pulse Width) = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time)

  • Page 199: Figure 11-13. Power-On Reset And Configuration Timings

    ELECTRICAL SPECIFICATIONS Figure 11-13. Power-On Reset and Configuration Timings = T15 (PWRGOOD Inactive Pulse Width) = T10 (RESET# Pulse Width) = T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time) Figure 11-14. Test Timings (Boundary Scan) = T43 (All Non-Test Inputs Setup Time) = T44 (All Non-Test Inputs Hold Time) = T40 (TDO Float Delay) = T37 (TDI, TMS Setup Time)

  • Page 200: 11.16. Flexible Motherboard Recommendations

    ELECTRICAL SPECIFICATIONS Figure 11-15. Test Reset Timing = T36 (TRST# Pulse Width) 11.16. FLEXIBLE MOTHERBOARD RECOMMENDATIONS Table 11-17 provides recommendations for designing a “flexible” motherboard for supporting future Pentium Pro processors. By meeting these recommendations, the same system design should be able to support all standard Pentium Pro processors. If the voltage regulator module is socketed using Header 8, a smaller range of support is required by the voltage regulator mod- ule.

  • Page 201: Gtl+ Interface Specification

    GTL+ Interface Specification...

  • Page 202: System Specification

    CHAPTER 12 GTL+ INTERFACE SPECIFICATION This section defines the new open-drain bus called GTL+. The primary target audience is de- signers developing systems using GTL+ devices such as the Pentium Pro processor and the 82450 PCIset. This specification will also be useful for I/O buffer designers developing an I/O cell and package to be used on a GTL+ bus.

  • Page 203: 12.1.1. System Dc Parameters

    GTL+ INTERFACE SPECIFICATION Figure 12-1. Example Terminated Bus with GTL+ Transceivers 12.1.1. System DC Parameters The following system DC parameters apply to Figure 12-1. 12-2...

  • Page 204: Table 12-1. System Dc Parameters

    GTL+ INTERFACE SPECIFICATION Table 12-1. System DC Parameters Symbol Parameter Value Tolerance Notes ±10% Termination Voltage 1.5V ±2% Input Reference Voltage 2/3 V 2 , 3 Termination Resistance (nominal) See Note Effective (Loaded) Network Impedance 45-65Ω NOTES: 1. This ±2% tolerance is in addition to the ±10% tolerance of V , and could be caused by such factors as voltage divider inaccuracy.

  • Page 205: 12.1.2. Topological Guidelines

    GTL+ INTERFACE SPECIFICATION 12.1.2. Topological Guidelines The board routing should use layout design rules consistent with high-speed digital design (i.e. minimize trace length and number of vias, minimize trace-to-trace coupling, maintain consistent impedance over the length of a net, maintain consistent impedance from one net to another, en- sure sufficient power to ground plane bypassing, etc.).

  • Page 206: Figure 12-2. Receiver Waveform Showing Signal Quality Parameters

    GTL+ INTERFACE SPECIFICATION Figure 12-2. Receiver Waveform Showing Signal Quality Parameters Table 12-3. Specifications for Signal Quality Symbol Parameter Specification Maximum Signal Maximum Absolute voltage a signal extends above V 0.3V Overshoot/Undershoot or below V (simulated w/o protection diodes). (guideline) Settling Limit The maximum amount of ringing, at the receiving chip ±10% of...

  • Page 207: Ringback Tolerance

    GTL+ INTERFACE SPECIFICATION The overshoot/undershoot guideline is provided to limit signals transitioning beyond V due to fast signal edge rates. Violating the overshoot/undershoot guideline is acceptable, but since excessive ringback is the harmful effect associated with overshoot/undershoot it will make satisfying the ringback specification very difficult.

  • Page 208: Figure 12-3. Standard Input Lo-To-Hi Waveform For Characterizing Receiver

    GTL+ INTERFACE SPECIFICATION 1.5 V Clk Ref τ 10 ps rise/fall Edges α + 0.2 φ ρ − 0.2 δ start Clock +0.05ns Time Figure 12-3. Standard Input Lo-to-Hi Waveform for Characterizing Receiver Ringback Tolerance start 1.5 V Clk Ref δ...

  • Page 209: 12.1.4. Ac Parameters: Flight Time

    GTL+ INTERFACE SPECIFICATION ρ & δ are respectively, the amplitude and duration of square-wave ringback, below the threshold voltage (V ), that the receiver can tolerate without increasing T by more than 0.05 ns for a given pair of (α, τ) values. If, for any reason, the receiver cannot tolerate any ringback across the reference threshold ), then ρ...

  • Page 210: Figure 12-5. Measuring Nominal Flight Time

    GTL+ INTERFACE SPECIFICATION The time difference between when a signal at the input pin of a receiving agent (adjusted to meet the receiver manufacturer’s conditions required for AC specifications) crosses V , and the time that the output pin of the driving agent crosses V were it driving the test load used by the manufacturer to specify that driver’s AC timings.

  • Page 211: Figure 12-6. Flight Time Of A Rising Edge Slower Than 0.3V/Ns

    GTL+ INTERFACE SPECIFICATION If either the rising or falling edge is slower than 0.3V/ns through the overdrive region beyond , (i.e., does not always stay ahead of an 0.3V/ns line), then the flight time for a rising edge is determined by extrapolating back from the signal crossing of V +200 mV to V using an 0.3V/ns slope as indicated in Figure 12-6.

  • Page 212: Figure 12-7. Extrapolated Flight Time Of A Non-Monotonic Rising Edge

    GTL+ INTERFACE SPECIFICATION Figure 12-7. Extrapolated Flight Time of a Non-Monotonic Rising Edge Figure 12-8. Extrapolated Flight Time of a Non-Monotonic Falling Edge 12-11...

  • Page 213: General Gtl+ I/O Buffer Specification

    GTL+ INTERFACE SPECIFICATION The maximum acceptable Flight Time is determined on a net-by-net basis, and is usually differ- ent for each unique driver-receiver pair. The maximum acceptable Flight Time can be calculated using the following equation (known as the setup time equation): <...

  • Page 214: 12.2.2. I/O Buffer Ac Specification

    GTL+ INTERFACE SPECIFICATION Table 12-4. I/O Buffer DC Parameters Symbol Parameter Units Notes Driver Output Low Voltage 0.600 Receiver Input High Voltage + 0.2 Receiver Input Low Voltage – 0.2 µA Input Leakage Current Total Input/Output Capacitance NOTES: 1. Measured into a 25Ω test load tied to V = 1.5 V, as shown in Figure 12-11.

  • Page 215: Table 12-5. I/O Buffer Ac Parameters

    GTL+ INTERFACE SPECIFICATION Table 12-5. I/O Buffer AC Parameters Symbol Parameter Units Figure Notes 1, 2, 3 dV/dt Output Signal Edge Rate, rise V/ns EDGE 1, 2, 3 dV/dt Output Signal Edge Rate, fall -0.8 V/ns EDGE 4, 5 Output Clock to Data Time no spec Figure 12-12 4, 6...

  • Page 216: Output Driver Acceptance Criteria

    GTL+ INTERFACE SPECIFICATION 12.2.2.1. OUTPUT DRIVER ACCEPTANCE CRITERIA Although Section 12.1.4., “AC Parameters: Flight Time” describes ways of amending flight time to a receiver when the edge rate is lower than the requirements shown in Table 12-5, or when there is excessive ringing, it is still preferable to avoid slow edge rates or excessive ringing through good driver and system design, hence the criteria presented in this section.

  • Page 217: Figure 12-9. Acceptable Driver Signal Quality

    GTL+ INTERFACE SPECIFICATION Figure 12-9. Acceptable Driver Signal Quality Figure 12-10. Unacceptable Signal, Due to Excessively Slow Edge After Crossing V 12-16...

  • Page 218: 12.2.3. Determining Clock-To-Out, Setup And Hold

    GTL+ INTERFACE SPECIFICATION ’ is the receiver’s hold time plus board clock driver and clock distribution skew minus the driver’s on-chip clock phase shift, clock distribution skew, and jitter, plus other data latch or JTAG delays (assuming these driver numbers are not included in the driver circuit simulation, as was done for setup in the above paragraph).

  • Page 219: Figure 12-11. Test Load For Measuring Output Ac Timings

    GTL+ INTERFACE SPECIFICATION Figure 12-11. Test Load for Measuring Output AC Timings measurement for a Lo-to-Hi signal transition is shown in Figure 12-12. The T measure- ment for Hi-to-Lo transitions is similar. Figure 12-12. Clock to Output Data Timing (T 12-18...

  • Page 220: Minimum Setup And Hold Times

    GTL+ INTERFACE SPECIFICATION 12.2.3.2. MINIMUM SETUP AND HOLD TIMES Setup time for GTL+ (T ) is defined as: The minimum time from the input signal pin crossing of V to the clock pin of the receiver crossing the 1.5 V level, which guarantees that the input buffer has captured new data at the input pin, given an infinite hold time.

  • Page 221: Figure 12-13. Standard Input Lo-To-Hi Waveform For Characterizing Receiver

    GTL+ INTERFACE SPECIFICATION 1.5 V Clk Ref + 0.2 − 0.2 Clock start Time Figure 12-13. Standard Input Lo-to-Hi Waveform for Characterizing Receiver Setup Time start 1.5 V Clk Ref + 0.2 − 0.2 Clock Time Figure 12-14. Standard Input Hi-to-Lo Waveform for Characterizing Receiver Setup Time 12-20...

  • Page 222: Receiver Ringback Tolerance

    GTL+ INTERFACE SPECIFICATION Hold time for GTL+, T , is defined as: HOLD The minimum time from the clock pin of the receivers crossing of the 1.5 V level to the receiver input signal pin crossing of V , which guarantees that the input buffer has captured new data at the receiver input signal pin, given an infinite setup time.

  • Page 223: System-Based Calculation Of Required Input And Output Timings

    GTL+ INTERFACE SPECIFICATION 12.2.4. System-Based Calculation of Required Input and Output Timings Below are two sample calculations. The first determines T and T , while the sec- CO-MAX SU-MIN ond determines T . These equations can be used for any system by replacing the as- HOLD-MIN sumptions listed below, with the actual system constraints.

  • Page 224: Package Specification

    GTL+ INTERFACE SPECIFICATION 12.2.5. Calculating Target T HOLD-MIN To calculate the longest possible minimum required hold time target value, assume that T CO-MIN is one fourth of T , and use the hold time equation given earlier. Note that Clock Jitter is CO-MAX not a part of the equation, since data is released by the driver and must be held at the receiver relative to the same clock edge:...

  • Page 225: 12.3.2. Package Capacitance

    GTL+ INTERFACE SPECIFICATION maximum package trace length cannot exceed 250 ps. If the PGA package is socketed, the max- imum package trace length would be ~225 ps since a typical PGA socket is around 25 ps in elec- trical length. For a QFP package, which typically requires a short stub on the PCB from the pad landing to a via (~50 ps), the package lead frame length should be less than ~200 ps.

  • Page 226: Figure 12-15. Ref8N Topology

    GTL+ INTERFACE SPECIFICATION REF8N Topology: 1.5 volts 1.5 volts 42 ohms 2 pF 42 ohms 2 pF 1.8 nS/ft. 1.8nS/ft. 0.5 in. 0.5 in. 0.10 in. 0.9 in. 0.07 in. 0.105 in. 0.10 in. 0.9 in. 0.07 in. 0.105 in. 72 ohms 72 ohms 1.02 nS/ft.

  • Page 227: 12.4.1. Ref8N Hspice Netlist

    GTL+ INTERFACE SPECIFICATION 12.4.1. Ref8N HSPICE Netlist $REF8N, Rev 1.1 Vpu vpu GND DC(vtt) rterm PU1 vpu (R=42)$ Pull-up termination resistance crterm PU1 vpu 2PF $ Pull-up termination capacitance TPU PU1 0 line1 0 Z0=72 TD=.075NS$ PCB link terminator to load 1 X1 line1 load1 socket$ Socket model T1 load1 0 load1a 0 Z0=42 TD=230PS $ CPU package model T2 load1a 0 CPU_1 0 Z0=200 TD=8.5PS$ Bondwire...
  • Page 228 GTL+ INTERFACE SPECIFICATION T15 line5 0 line6 0 Z0=72 TD=403PS$ PCB trace between packages T16 line6 0 load6 0 Z0=50 TD=50PS$ PCB trace from via to landing pad T17 load6 0 asic_4 0 Z0=75 TD=180PS$ ASIC package CASIC_4 asic_4 0 6.5PF$ ASIC input capacitance T18 line6 0 line7 0 Z0=72 TD=403PS $ PCB trace between packages X3 line7 load7 socket$ Socket model T19 load7 0 load7a 0 Z0=42 TD=230PS$ CPU worst case package...

  • Page 229: Tolerant Signal Quality Specifications

    3.3V Tolerant Signal Quality Specifications...

  • Page 230: Overshoot/Undershoot Guidelines

    They are Overshoot/Undershoot, Ringback and Settling Limit. All three signal ® quality parameters are shown in Figure 13-1. The Pentium Pro Processor I/O Buffer Mod- els—IBIS Format (on world wide web page www.intel.com) contain models for simulating 3.3V tolerant signal distribution. 13.1. OVERSHOOT/UNDERSHOOT GUIDELINES Overshoot (or undershoot) is the absolute value of the maximum voltage allowed above the nom- inal high voltage or below V SS .

  • Page 231: Ringback Specification

    3.3V TOLERANT SIGNAL QUALITY SPECIFICATIONS Settling Limit Overshoot 3.3V Rising-edge Ringback Falling-edge Ringback Settling Limit Time Undershoot Figure 13-1. 3.3V Tolerant Signal Overshoot/Undershoot and Ringback 13.2. RINGBACK SPECIFICATION Ringback refers to the amount of reflection seen after a signal has undergone a transition. The ringback specification is the voltage that the signal rings back to after achieving its farthest ex- cursion.

  • Page 232: Settling Limit Guideline

    3.3V TOLERANT SIGNAL QUALITY SPECIFICATIONS 13.3. SETTLING LIMIT GUIDELINE A Settling Limit defines the maximum amount of ringing at the receiving pin that a signal must be limited to before its next transition. The amount allowed is 10% of the total signal swing (V HI -V LO ) above and below its final value.

  • Page 233: Thermal Specifications

    Thermal Specifications...

  • Page 234: Thermal Parameters

    Table 11-5 specifies the Pentium Pro processor power dissipation. It is highly recommended that systems be designed to dissipate at least 40W per processor to allow the same design to accom- modate higher frequency or otherwise enhanced members of the Pentium Pro family. 14.1.

  • Page 235: Figure 14-1. Location Of Case Temperature Measurement (Top-Side View)

    THERMAL SPECIFICATIONS 2.66” 1.23” CPU Die L2 Cache Die 2.46” 0.80” Figure 14-1. Location of Case Temperature Measurement (Top-Side View) Thermal Interface Heat Sink Material Probe Heat Spreader Ceramic Package Ceramic Package Figure 14-2. Thermocouple Placement 14-2...

  • Page 236: 14.1.3. Thermal Resistance

    THERMAL SPECIFICATIONS 14.1.3. Thermal Resistance The thermal resistance value for the case-to-ambient, Θ CA , is used as a measure of the cooling solution’s thermal performance. Θ CA is comprised of the case-to-sink thermal resistance, Θ CS , and the sink-to-ambient thermal resistance, Θ SA . Θ CS is a measure of the thermal resistance along the heat flow path from the top of the IC package to the bottom of the thermal cooling solution.

  • Page 237: Thermal Analysis

    THERMAL SPECIFICATIONS 14.2. THERMAL ANALYSIS Table 14-1 below lists the case-to-ambient thermal resistances of the Pentium Pro processor for different air flow rates and heat sink heights. Table 14-1. Case-To-Ambient Thermal Resistance ° Θ CA [ C/W] vs. Airflow [Linear Feet per Minute] and Heat Sink Height 1 Airflow (LFM): 1000 With 0.5”...

  • Page 238: Table 14-2. Ambient Temperatures Required At Heat Sink For 29.2W And 85° Case

    THERMAL SPECIFICATIONS Table 14-2. Ambient Temperatures Required at Heat Sink for 29.2W and 85° Case T A vs. Airflow [Linear Feet per Minute] and Heat Sink Height 1 Airflow (LFM): 1000 With 0.5” Heat Sink 2 — With 1.0” Heat Sink 2 With 1.5”...

  • Page 239: Mechanical Specifications

    Mechanical Specifications...

  • Page 240: Dimensions

    V CC S, V CC 5and V SS locations shown. Be sure to read Chapter 17, OverDrive® Processor Socket Specification for the mechanical constraints for the OverDrive processor. Also, in- vestigate the tools that will be used for debug before laying out the system. Intel’s tools are described in Chapter 16, Tools.

  • Page 241: Figure 15-1. Package Dimensions-Bottom View

    MECHANICAL SPECIFICATIONS Figure 15-1. Package Dimensions-Bottom View 15-2...

  • Page 242: Figure 15-2. Top View Of Keep Out Zones And Heat Spreader

    MECHANICAL SPECIFICATIONS 2.46 ± 0.10" 1.30 ± 0.10" HEAT SPREADER 2.66 ± 0.10" AAAA AAAA 2.225 ± 0.10" AAAA AAAA AAAA AAAA AAAA AAAA Keep Out Zones AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 1.025" AAAA AAAA AAAA...

  • Page 243: Pinout

    MECHANICAL SPECIFICATIONS 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA...

  • Page 244: Table 15-2. Pin Listing In Pin # Order

    MECHANICAL SPECIFICATIONS Table 15-2. Pin Listing in Pin # Order Pin # Signal Name Pin # Signal Name Pin # Signal Name VREF0 VCCP A33# STPCLK# A34# VCCP D22# TRST# D23# IGNNE# VCCP D25# A20M# D24# A35# D26# FLUSH# IERR# VCCP THERMTRIP# BERR#...
  • Page 245 MECHANICAL SPECIFICATIONS Table 15-2. Pin Listing in Pin # Order (Contd.) Pin # Signal Name Pin # Signal Name Pin # Signal Name D33# AP0# D34# RSP# VCCP BPRI# VCCP BNR# VCCP BR3# DEP7# VREF6 D60# VCCP D56# A10# D55# RESERVED D51# SMI#...
  • Page 246 MECHANICAL SPECIFICATIONS Table 15-2. Pin Listing in Pin # Order (Contd.) Pin # Signal Name Pin # Signal Name Pin # Signal Name PRDY# RESERVED AJ39 RESET# ADS# AJ41 VCCP DEP1# RS1# AJ43 DEP6# RS2# AJ45 VCCP D62# AERR# AJ47 BR2# AE39 TESTHI...
  • Page 247 MECHANICAL SPECIFICATIONS Table 15-2. Pin Listing in Pin # Order (Contd.) Pin # Signal Name Pin # Signal Name Pin # Signal Name AQ45 AW45 VCCS BA37 TESTLO AQ47 VCCP AW47 BA39 VID0 VCCS BA41 VCCS VID1 VCCS BA43 VID2 VCCS BA45 VCCS...

  • Page 248: Table 15-3. Pin Listing In Alphabetic Order

    MECHANICAL SPECIFICATIONS Table 15-3. Pin Listing in Alphabetic Order Signal Name Pin # Signal Name Pin # Signal Name Pin # A35# D14# ADS# D15# AERR# D16# AP0# D17# AP1# D18# BCLK D19# BERR# D20# A10# BINIT# AC43 D21# A11# BNR# D22# A12#...
  • Page 249 MECHANICAL SPECIFICATIONS Table 15-3. Pin Listing in Alphabetic Order (Contd.) Signal Name Pin # Signal Name Pin # Signal Name Pin # D47# IERR# RESERVED BC35 D48# IGNNE# RESET# D49# INIT# D50# LINT0/INTR AG43 RS0# D51# LINT1/NMI AG41 RS1# D52# LOCK# RS2# D53#...
  • Page 250 MECHANICAL SPECIFICATIONS Table 15-3. Pin Listing in Alphabetic Order (Contd.) Signal Name Pin # Signal Name Pin # Signal Name Pin # VCC5 VCCP AL47 VCCS AY45 VCCP VCCP VCCS AY47 VCCP VCCP VCCS VCCP VCCP AN41 VCCS VCCP VCCP AN45 VCCS BA41...
  • Page 251 MECHANICAL SPECIFICATIONS Table 15-3. Pin Listing in Alphabetic Order (Contd.) Signal Name Pin # Signal Name Pin # Signal Name Pin # AF40 AF42 AW39 AF44 AW43 AF46 AW47 AJ39 BA19 AJ43 BA23 AJ47 BA27 BA31 BA39 AL41 BA43 AL45 BA47 AN39 AN43...
  • Page 252 Tools...

  • Page 253: Analog Modeling

    Included here is a discussion on the Pentium Pro processor I/O buffer models and a description of the Intel recommended debug port implementation. A debug port is used to connect a debug tool to a target system in order to provide run-time control over program execution, regis- ter/memory/IO access and breakpoints.

  • Page 254: 16.2.1. Primary Function

    I/O. 16.2.2. Debug Port Connector Description An ITP will connect to the Pentium Pro processor system through the debug port. Intel recom- mended connectors, to mate an ITP cable with the debug port on your board, are available in either a vertical or right-angle configuration.

  • Page 255: 16.2.4. Signal Notes

    TOOLS Table 16-1. Debug Port Pinout (Contd.) Name Description DBINST# Indicates to user system that the ITP is installed (from ITP GND). See signal note 4 TRST# Boundary scan signal from ITP to MP cluster BSEN# ITP asserts BSEN# while using Boundary Scan PREQ0# PREQ# signal from ITP to CPU 0 ®...

  • Page 256: Signal Note 1: Reset#, Prdyx

    TOOLS 16.2.4.1. SIGNAL NOTE 1: RESET#, PRDYX# RESET# and PRDY# are GTL+ signals that come from the Pentium Pro processor system to the debug port; they are not driven by an ITP from the debug port. Adding inches of transmission line on to the RESET# or PRDY# signals after they are past the final Pentium Pro processor bus load does not change the timing calculations for the Pentium Pro processor bus agents.

  • Page 257: Signal Note 7: Trst

    TOOLS 16.2.4.7. SIGNAL NOTE 7: TRST# If the TRST# signal is connected to the 82454GX, it should be pulled down through a 470 ohm resistor. 16.2.4.8. SIGNAL NOTE 8: TCK *WARNING: A significant number of target systems have signal integrity issues with the TCK signal.

  • Page 258: Signal Note 9: Tms

    TOOLS If the signal is more easily routed in a star configuration, each leg that is greater than 8" in length should be terminated with a resistor value R, where: R = (62 ohms) x (the number of legs greater than 8 inches).

  • Page 259: 16.2.5. Debug Port Layout

    TOOLS 16.2.5. Debug Port Layout Figure 16-4 shows the simplest way to layout the debug port in a multiprocessor system. In this example, the four processors are the only components in the system boundary scan chain. Sys- tems incorporating boundary scan for use other than for an ITP should consider providing a method to partition the boundary scan chain in two distinct sections;...

  • Page 260: Figure 16-4. Generic Mp System Layout For Debug Port Connection

    TOOLS Figure 16-4. Generic MP System Layout for Debug Port Connection 16-8...

  • Page 261: Signal Quality Notes

    TOOLS 16.2.5.1. SIGNAL QUALITY NOTES If system signals to the debug port (i.e. TDO, PRDY[0-3]# and RESET#) are used elsewhere in the system, then dedicated drivers should be used to isolate the signals from reflections coming from the end of the debug port cable. If the Pentium Pro processor boundary scan signals are used elsewhere in the system, then the TDI, TMS, TCK, and TRST# signals from the debug port should be isolated from the system signals with multiplexers as discussed in Section 16.2.5., “Debug Port Layout”.

  • Page 262: Using Boundary Scan To Communicate To The Pentium Pro Processor

    TOOLS Figure 16-6. Hole Layout for Connector on Primary Side of Circuit Board ® 16.2.6. Using Boundary Scan to Communicate to the Pentium Pro Processor An ITP communicates to the processors in a Pentium Pro processor system by stopping their ex- ecution and sending/receiving messages over their boundary scan pins.

  • Page 263: Figure 16-8. Pentium ® Pro Processor-Based System Where Boundary Scan Is Used

    TOOLS While an ITP requires only that the Pentium Pro processors be in the scan chain, Figure 16-8 shows a more complex case. The order in which you place the components in your scan chain is up to you. However, you may need to provide scan chain layout information to the ITP so it knows where the CPUs are in the chain.

  • Page 264: Overdrive ® Processor Socket Specification

    ® OverDrive Processor Socket Specification...

  • Page 265: Introduction

    Header 8 can be populated with an OEM Pentium Pro processor VRM or with the OverDrive VRM which Intel plans to ship with the OverDrive processor as part of the retail package. The OverDrive processor will also support Voltage Identification as described in Section 11.6., “Voltage Identification”.

  • Page 266: Mechanical Specifications

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Socket 8: 387-pin SPGA Zero Insertion Force (ZIF) socket defined to contain either a Pentium Pro or OverDrive processor. 17.2. MECHANICAL SPECIFICATIONS This section specifies the mechanical features of Socket 8 and Header 8. This section includes the pinout, surrounding space requirements, and standardized clip attachment features.

  • Page 267: Vendor Contacts For Socket 8 And Header 8

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 17.2.1. Vendor Contacts for Socket 8 and Header 8 Contact your local Intel representative for a list of participating Socket 8 and Header 8 suppliers. 17.2.2. Socket 8 Definition Socket 8 is a 387-pin, modified staggered pin grid array (SPGA), Zero Insertion Force (ZIF) socket.

  • Page 268: Socket 8 Space Requirements

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Table 17-1. OverDrive ® Processor Signal Descriptions Pin Name 1 Pin # Function V cc 5 Input +5V Supply required for OverDrive ® processor fan/heatsink. Output This output is tied to V ss in the OverDrive processor to indicate the presence of an upgrade processor.

  • Page 269: Figure 17-3. Overdrive ® Processor Envelope Dimensions

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 3.23" 1.45" 0.58" Pin A 1 2.46" END V IEW TO P VIEW OverDri KEEP OUT ZONES NOT SHOW N SIDE V IEW 0.50" Figure 17-3. OverDrive ® Processor Envelope Dimensions “Keep out zones,” also shown in Figure 17-4, have been established around the heat sink clip attachment tabs to prevent damage to surface mounted components during clip installation and removal.
  • Page 270 OVERDRIVE® PROCESSOR SOCKET SPECIFICATION For designs which use Header 8, the header itself can violate the 0.2” airspace around the Over- Drive processor package. A VRM (either Pentium Pro processor VRM or OverDrive VRM), once installed in Header 8, and any components on the module, MUST NOT violate the 0.2” airspace.

  • Page 271: Socket 8 Clip Attachment Tabs

    Details of the clip attachment tabs and overall dimensions of Intel qualified sockets may be ob- tained from participating socket suppliers.

  • Page 272: Overdrive ® Voltage Regulator Module Definition

    OVERDRIVE VRM REQUIREMENT When upgrading with an OverDrive processor, Intel suggests the use of its matched Voltage Reg- ulator Module, which Intel plans to ship with the OverDrive processor retail package. If the OEM includes on-board voltage regulation and the Header 8 for the OverDrive VRM, the on-board voltage regulator must be shut off via the UP# output of the CPU.

  • Page 273: Figure 17-5. Header 8 Pinout

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Pin # Signal Name Pin # Signal Name 5Vin 5Vin 5Vin 5Vin 5Vin 5Vin 12Vin 12Vin Reserved Reserved Reserved OUTEN VID0 VID1 VID2 VID3 PwrGood Vcc P Vcc P Vcc P Vcc P Vcc P Vcc P Vcc P Vcc P Vcc P...

  • Page 274: Overdrive Vrm Space Requirements

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Table 17-2. Header 8 Pin Reference Pin Name Usage Function 12Vin Input Required +12V±5% Supply +5V±5% Supply 1 5Vin Input Required V ss Input Required Ground Reference OUTEN Input Optional When driven high this input will enable the OEM VRM output and float the OverDrive ®...

  • Page 275: Functional Operation Of Overdrive

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 0.80 0.14 3.10 Max VRM PCB Width Max Component Max Component Height on front Height on back of VRM PCB of VRM PCB Total height from Total space motherboard for VRM / OverDrive VRM PCB to an Header 8 immovable from...

  • Page 276: Figure 17-7. Upgrade Presence Detect Schematic - Case 1

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION OverDrive processor and the OEM VRM is NOT replaced with the OverDrive VRM, the original voltage regulator will never enable its outputs because the lower voltage OverDrive processor could be damaged. Refer to Figure 17-7. + 5 Volt 10 k Ω...

  • Page 277: 17.3.3. Bios Considerations

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION — Case 3: Alternate voltage source only If the system is designed with only a programmable voltage source using the VID3- VID0 pins, then the UP# signal need not be used. NOTE The programmable voltage source needs to be able to provide the OverDrive processor with it’s required power.

  • Page 278: Overdrive ® Processor Cpuid

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION ® 17.3.3.1. OVERDRIVE PROCESSOR CPUID Following power-on RESET or the CPUID instruction, the EAX register contains the values shown in Table 17-3. ® Table 17-3. OverDrive Processor CPUID Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] 17.3.3.2.

  • Page 279: Overdrive ® Processor D.c. Specifications

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 17.4.1. D.C. Specifications ® 17.4.1.1. OVERDRIVE PROCESSOR D.C. SPECIFICATIONS Table 17-4 lists the D.C. specifications for the OverDrive processor that are either different from or in addition to the Pentium Pro processor specifications. ® Table 17-4. OverDrive Processor D.C.

  • Page 280: Overdrive ® Vrm D.c. Specifications

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION ® 17.4.1.2. OVERDRIVE VRM D.C. SPECIFICATIONS The D.C. specifications for the OverDrive VRM are presented in Table 17-5. Table 17-5. OverDrive ® VRM Specifications 5Vin = 5V ± 5%, T CASE = 0 to 105º C Symbol Parameter Unit...

  • Page 281: 17.4.3. A.c. Specifications

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 17.4.3. A.C. Specifications Except for internal CPU core Clock frequency, the OverDrive processor will operate within the same A.C. specifications as the Pentium Pro processor. 17.5. THERMAL SPECIFICATIONS This section describes the cooling solution utilized by the OverDrive processor and the cool- ing requirements for both the processor and VRM.

  • Page 282: Overdrive ® Vrm Cooling Requirements

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION • If an OEM fan/heatsink is used, then electrical connections between the OEM fan/heatsink and system must be through an end user separable connector. • If an OEM fan/heatsink is used, removal of the assembly must not interfere with the operation of the OverDrive processor, for example, by activating cooling failure protection mechanisms employed by the OEM.

  • Page 283: Criteria For Overdrive Processor

    The diagrams and checklists will aid the OEM to check specific criteria. Several design tools are available through Intel field representatives which will help the OEM meet the criteria. Refer to Section 17.6.1., “Related Documents”.

  • Page 284: 17.6.1. Related Documents

    17.6.1. Related Documents All references to related documents within this section imply the latest published revision of the related document, unless specifically stated otherwise. Contact your local Intel Sales represen- tative for latest revisions of the related documents. Processor and Motherboard Documentation: •...

  • Page 285: Table 17-8. Electrical Test Criteria For Systems Employing Header 8

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Table 17-8. Electrical Test Criteria for Systems Employing Header 8 Criteria Refer To: Comment 5Vin Tolerance Table 17-2 Measured Under the following Loading Conditions: Header 8 Input • Max Icc 5 at Steady-State • Min Icc 5 at Steady-State •...

  • Page 286: Pentium ® Pro Processor Electrical Criteria

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION The criteria for the OverDrive processor that apply to all motherboards and systems are present- ed in Table 17-10. Table 17-10. Electrical Test Criteria for all Systems Criteria Refer To: Comment Vcc S Table 17-4 Loading Conditions: Secondary CPU Vcc Voltage •...

  • Page 287: Overdrive ® Processor Cooling Requirements (Systems Testing Only)

    OVERDRIVE® PROCESSOR SOCKET SPECIFICATION ® 17.6.3.2. PENTIUM PRO PROCESSOR COOLING REQUIREMENTS (SYSTEMS TESTING ONLY) The Pentium Pro processor case temperature must meet the specifications of the Pentium Pro processor. Thermal testing should be performed under worst case thermal loading (Refer to Section 17.6.3.1., “OverDrive®...

  • Page 288: Overdrive ® Vrm Clearance And Airspace Requirements

    BIOS Functionality Section • CPU Type Reported on Screen must be reported correctly 17.3.3. or not at all. Intel recommends reporting “OverDrive ® Processor”. • Never Use Timing Loops. • Do not test the cache, or use model specific registers when the upgrade is detected.

  • Page 289: 17.6.6. End User Criteria

    To ensure processor upgradability, a system should employ the following Intel-qualified Over- Drive processor components. For a list of qualified components contact your Intel sales repre- sentative, or if in the US, contact Intel FaxBACK Information Service at (800) 525-3019.
  • Page 290 Signals Reference...

  • Page 291: Appendix Asignals Reference

    APPENDIX A SIGNALS REFERENCE This appendix provides an alphabetical listing of all Pentium Pro processor signals. The tables at the end of this appendix summarize the signals by direction: output, input, and I/O. A.1. ALPHABETICAL SIGNALS REFERENCE A.1.1. A[35:3]# (I/O) The A[35:3]# signals are the address signals.

  • Page 292: A20M# (I

    SIGNALS REFERENCE During the second clock of the Request Phase, Ab[35:3]# signals perform identical signal func- tions for all transactions. For ease of description, these functions are described using new signal names. Ab[31:24]# are renamed the attribute signals ATTR[7:0]#. Ab[23:16]# are renamed the Deferred ID signals DID[7:0]#.

  • Page 293: Aerr# (I/O

    SIGNALS REFERENCE If the request initiator continues to own the bus after the first Request Phase, it can issue a new request every three clocks. If the request initiator needs to release the bus ownership after the Request Phase, it can deactivate its BREQn#/ BPRI# arbitration signal as early as with the acti- vation of ADS#.

  • Page 294: Table A-1. Asz[1:0]# Signal Decode

    SIGNALS REFERENCE A.1.5. AP[1:0]# (I/O) The AP[1:0]# signals are the address parity signals. They are driven by the request initiator dur- ing the two Request Phase clocks along with ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# cov- ers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low.

  • Page 295: Table A-2. Attr[7:0]# Field Descriptions

    SIGNALS REFERENCE Table A-2. ATTR[7:0]# Field Descriptions ATTR[7:3]# ATTR[2]# ATTR[1:0]# Potentially Reserved (0) Speculatable WriteBack WriteProtect WriteThrough UnCacheable A.1.8. BCLK (I) The BCLK (clock) signal is the Execution Control group input signal. It determines the bus fre- quency. All agents drive their outputs and latch their inputs on the BCLK rising edge. The BCLK signal indirectly determines the Pentium Pro processor’s internal clock frequency.

  • Page 296: A.1.10. Berr# (I/O)

    SIGNALS REFERENCE For Deferred Reply, Interrupt Acknowledge, and Branch Trace Message transactions, the BE[7:0]# signals are undefined. A.1.10. BERR# (I/O) The BERR# signal is the Error group Bus Error signal. It is asserted to indicate an unrecoverable error without a bus protocol violation. The BERR# protocol is as follows: If an agent detects an unrecoverable error for which BERR# is a valid error response and BERR# is sampled inactive, it asserts BERR# for three clocks.

  • Page 297: A.1.12. Bnr# (I/O)

    SIGNALS REFERENCE A.1.12. BNR# (I/O) The BNR# signal is the Block Next Request signal in the Arbitration group. The BNR# signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions to avoid an internal transaction queue overflow.

  • Page 298: Table A-4. Br0#(I/O), Br1#, Br2#, Br3# Signals Rotating Interconnect

    SIGNALS REFERENCE A.1.15. BPRI# (I) The BPRI# signal is the Priority-agent Bus Request signal. The priority agent arbitrates for the bus by asserting BPRI#. The priority agent is always be the next bus owner. Observing BPRI# active causes the current symmetric owner to stop issuing new requests, unless such requests are part of an ongoing locked operation.

  • Page 299: Table A-5. Br[3:0]# Signal Agent Ids

    SIGNALS REFERENCE During power-up configuration, the central agent must assert the BR0# bus signal. All symmet- ric agents sample their BR[3:0]# pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent ID. All agents then configure their pins to match the appropriate bus signal protocol, as shown in Table A-5.

  • Page 300: A.1.18. D[63:0]# (I/O)

    SIGNALS REFERENCE A.1.18. D[63:0]# (I/O) The D[63:0]# signals are the data signals. They are driven during the Data Phase by the agent responsible for driving the data. These signals provide a 64-bit data path between various Pen- tium Pro processor bus agents. 32-byte line transfers require four data transfer clocks with valid data on all eight bytes.

  • Page 301: A.1.21. Den# (I/0)

    SIGNALS REFERENCE If DEFER# is inactive, or HITM# is active, then the transaction is committed for in-order com- pletion and snoop ownership is transferred normally between the requesting agent, the snooping agents, and the response agent. If DEFER# is active with HITM# inactive, the transaction commitment is deferred. If the defer agent completes the transaction with a retry response, the requesting agent must retry the trans- action.

  • Page 302: Table A-6. Did[7:0]# Encoding

    SIGNALS REFERENCE The deferred identifier defines the token supplied by the request initiator. DID[7:4]# carry the request initiators’ agent identifier and DID[3:0]# carry a transaction identifier associated with the request. This configuration limits the bus specification to 16 bus masters with each one of the bus masters capable of making up to sixteen requests.

  • Page 303: Table A-7. Efx[4:0]# Signal Definitions

    SIGNALS REFERENCE A.1.26. EXF[4:0]# (I/O) The EXF[4:0]# signals are the Extended Function signals. They are transferred on the Ab[7:3]# signals by the request initiator during the second clock of the Request Phase. The signals specify any special functional requirement associated with the transaction based on the requestor mode or capability.

  • Page 304: A.1.29. Frcerr(I/O)

    SIGNALS REFERENCE A.1.29. FRCERR(I/O) The FRCERR signal is the Error group Functional-redundancy-check Error signal. If two Pen- tium Pro processors are configured in an FRC pair, as a single “logical” processor, then the checker processor asserts FRCERR if it detects a mismatch between its internally sampled out- puts and the master processor’s outputs.

  • Page 305: A.1.31. Ierr# (O)

    The processor continues to handle snoop requests during INIT# assertion. INIT# can be used to help performance of DOS extenders written for the Intel 80286 processor. INIT# provides a method to switch from protected mode to real mode while maintaining the contents of the internal caches and floating-point state.

  • Page 306: Table A-8. Len[1:0]# Signals Data Transfer Lengths

    SIGNALS REFERENCE A.1.34. INTR (I) The INTR signal is the Interrupt Request signal. The INTR input indicates that an external in- terrupt has been generated. The interrupt is maskable using the IF bit in the EFLAGS register. If the IF bit is set, the Pentium Pro processor vectors to the interrupt handler after the current in- struction execution is completed.

  • Page 307: A.1.37. Lock# (I/O)

    SIGNALS REFERENCE Both of these signals must be software configured by programming the APIC register space to be used either as NMI/INTR or LINT[1:0] in the BIOS. Because APIC is enabled after reset, LINT[1:0] is the default configuration. A.1.37. LOCK# (I/O) The LOCK# signal is the Arbitration group bus lock signal.

  • Page 308: Table A-9. Transaction Types Defined By Reqa#/Reqb# Signals

    SIGNALS REFERENCE A.1.41. PWR_GD (I) PWR_GD is driven to the Pentium Pro processor by the system to indicate that the clocks and power supplies are within their specification. This signal is used within the Pentium Pro processor to protect circuits against voltage sequenc- ing issues.

  • Page 309: A.1.43. Reset# (I)

    SIGNALS REFERENCE Table A-9. Transaction Types Defined by REQa#/REQb# Signals REQa[4:0]# REQb[4:0]# Transaction I/O Write DSZ# LEN# Rsvd (Ignore) DSZ# Memory Read & ASZ# DSZ# LEN# Invalidate Rsvd (Memory Write) ASZ# DSZ# LEN# Memory Code Read ASZ# D/C#= DSZ# LEN# Memory Data Read ASZ# D/C#=...

  • Page 310: Table A-10. Transaction Response Encodings

    SIGNALS REFERENCE A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This definition allows parity to be high when all covered sig- nals are high. A.1.45.

  • Page 311: A.1.46. Rsp# (I)

    SIGNALS REFERENCE The response agent returns a Normal without data response for a write transaction with • HITM# and DEFER# deasserted in the Snoop Phase, when the addressed agent samples TRDY# active and DBSY# inactive, and it is ready to complete the transaction. The response agent must return an Implicit writeback response in the next clock for a read •...

  • Page 312: A.1.49. Splck# (I/O)

    SIGNALS REFERENCE A.1.49. SPLCK# (I/O) The SPLCK# signal is the Split Lock signal. It is driven in the second clock of the Request Phase on the EXF3#/Ab6# signal of the first transaction of a locked operation. It is driven to indicate that the locked operation will consist of four locked transactions.

  • Page 313: A.1.55. Trdy# (I)

    SIGNALS REFERENCE A.1.55. TRDY# (I) The TRDY# signal is the target Ready signal. It is asserted by the target in the Response Phase to indicate that the target is ready to receive write or implicit writeback data transfer. This en- ables the request initiator or the snooping agent to begin the appropriate data transfer.

  • Page 314: A.2. Signal Summaries

    SIGNALS REFERENCE A.2. SIGNAL SUMMARIES The following tables list attributes of the Pentium Pro processor output, input, and I/O signals. Table A-11. Output Signals Name Active Level Clock Signal Group FERR# Asynch PC compatibility IERR# Asynch Implementation PRDY# BCLK Implementation High JTAG THERMTRIP#...

  • Page 315: Table A-12. Input Signals

    SIGNALS REFERENCE Table A-12. Input Signals 1 (Contd.) Name Active Level Clock Signal Group Qualified RESET# High BCLK Pentium Pro Always processor bus RS[2:0]# BCLK Pentium Pro Always processor bus RSP# BCLK Pentium Pro Always processor bus SMI# Asynch PC compatibility STPCLK# Asynch Implementation...
  • Page 316 SIGNALS REFERENCE Table A-13. Input/Output Signals (Single Driver)(Contd.) Name Active Level Clock Signal Group Qualified D[63:0]# BCLK Pentium Pro DRDY# processor bus DBSY# BCLK Pentium Pro Always processor bus DEN# BCLK Pentium Pro ADS# + 1 processor bus DEP[7:0]# BCLK Pentium Pro DRDY# processor bus...

  • Page 317: Table A-14. Input/Output Signals (Multiple Driver)

    SIGNALS REFERENCE Table A-14. Input/Output Signals (Multiple Driver) Name Active Level Clock Signal Group Qualified AERR# BCLK Pentium ® ADS# + 3 processor bus BNR# BCLK Pentium Pro Always processor bus BERR# BCLK Pentium Pro Always processor bus BINIT# BCLK Pentium Pro Always processor bus...
  • Page 318 SYSTEMS QUALITY/RELIABILITY 231762 1-55512-046-6 A complete set of this information is available on CD-ROM through Intel’s Data on Demand program, order number 240897. For information about Intel’s Data on Demand ask for item number 240952. January 1996 Order Number: 000900-001...

  • Page 319: Intel Literature Centers

    World Wide Web [URL: http://www.intel.com/] Intel’s Web site now contains technical and product information that is available 24 hours a day! Also visit Intel’s site for financials, history, current news and events, job opportunities, educational news and much, much more!
  • Page 320 Index...
  • Page 321 INDEX BERR# signal ..... 3-22 Driving policy ......9-3 A20M# signal .
  • Page 322 INDEX Lock signal Configuration options ....9-1 Protocol rules ....4-18 Conventions .
  • Page 323 Flush Acknowledge Transaction ...5-11 – Intel Platform Support Program ..17-19 17-25 Flush Transaction..... . .5-10 Internal access, definition of .
  • Page 324 INDEX Interrupt Acknowledge Transaction ..5-8 Memory Write Transaction ....5-5 Interrupt Request signal ....A-16 Memory (Read) Invalidate Transaction .
  • Page 325 INDEX PICD[1:0] signals ....3-11 A-17 RESET# input signal ....3-10 A-19 Pin Listing in Pin # Order .
  • Page 326 INDEX Bus signals ......4-21 Test-data-out signal ....A-22 Completion .
  • Page 327 INDEX Waveforms ......11-24 WB (writeback) memory type ..6-2 Wired-OR glitch .

Table of Contents