Intel PXA255 Developer's Manual page 62

System Architecture
Table 2-8. System Architecture Register Address Summary (Sheet 12 of 12)
Unit Address
0x4800_0000
0x4800_0004
0x4800_0008
0x4800_000C
0x4800_0010
0x4800_0014
0x4800_001C
0x4800_0024
0x4800_0028
0x4800_002C
0x4800_0030
0x4800_0034
0x4800_0038
0x4800_003C
0x4800_0040
0x4800_0044
0x4800_0058
0x4800_0064
2-32
Register Symbol
MDCNFG SDRAM Configuration Register 0
MDREFR SDRAM Refresh Control Register
MSC0 Static Memory Control Register 0
MSC1 Static Memory Control Register 1
MSC2 Static Memory Control Register 2
Expansion Memory (PCMCIA/Compact Flash) Bus Configuration
MECR
Register
SXCNFG Synchronous Static Memory Control Register
SXMRS MRS value to be written to SMROM
MCMEM0 Card interface Common Memory Space Socket 0 Timing Configuration
MCMEM1 Card interface Common Memory Space Socket 1 Timing Configuration
MCATT0 Card interface Attribute Space Socket 0 Timing Configuration
MCATT1 Card interface Attribute Space Socket 1 Timing Configuration
MCIO0 Card interface I/O Space Socket 0 Timing Configuration
MCIO1 Card interface I/O Space Socket 1 Timing Configuration
MDMRS MRS value to be written to SDRAM
Read-only Boot-Time Register. Contains BOOT_SEL and PKG SEL
BOOT_DEF
values.
MDMRSLP Low Power SDRAM Mode Register Set Configuration Register
SA1111CR SA1111 Compatibility Register
Register Description
Intel® PXA255 Processor Developer's Manual