Lcr Bit Definitions - Intel PXA255 Developer's Manual

UARTs
Table 10-12. LCR Bit Definitions
Base+0x0C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:8
7 DLAB
6
5 STKYP
4
3
2
1:0 WLS[1:0]
10-14
Line Control Register
reserved
0 0 0 0 0 0 0
— reserved
Divisor Latch Access Bit: Must be set high (logic 1) to access the Divisor Latches of the
Baud Rate Generator during a READ or WRITE operation. Must be set low (logic 0) to
access the Receiver Buffer, the Transmit Holding Register, or the IER.
0 – access Transmit Holding register (THR), Receive Buffer register (RBR) and IER.
1 – access Divisor Latch registers (DLL and DLH)
Set Break: Causes a break condition to be transmitted to the receiving UART. Acts only on
the TXD pin and has no effect on the transmitter logic. In FIFO mode, wait until the
transmitter is idle, LSR[TEMT]=1, to set and clear SB.
SB
0 – no effect on TXD output
1 – forces TXD output to 0 (space)
Sticky Parity: Forces the bit value at the parity bit location to be the opposite of the EPS bit,
rather than the parity value. This stops parity generation. If PEN = 0, STKYP is ignored.
0 – no effect on parity bit
1 – forces parity bit to be opposite of EPS bit value
Even Parity Select: Even parity select bit. If PEN = 0, EPS is ignored.
EPS
0 – sends or checks for odd parity
1 – sends or checks for even parity
Parity Enable: Enables a parity bit to be generated on transmission or checked on
reception.
PEN
0 – no parity
1 – parity
Stop Bits: Specifies the number of stop bits transmitted and received in each character.
When receiving, the receiver only checks the first stop bit.
STB
0 – 1 stop bit
1 – 2 stop bits, except for 5-bit character then 1-1/2 bits
Word Length Select: Specifies the number of data bits in each transmitted or received
character.
00 – 5-bit character
01 – 6-bit character
10 – 7-bit character
11 – 8-bit character
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
UART
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0