Intel PXA255 Developer's Manual page 57

Table 2-8. System Architecture Register Address Summary (Sheet 7 of 12)
Unit Address
0x4060_0068
0x4060_006C
0x4060_0070
0x4060_0074
0x4060_0078
0x4060_007C
0x4060_0080
0x4060_0100
0x4060_0180
0x4060_0200
0x4060_0400
0x4060_00A0
0x4060_0600
0x4060_0680
0x4060_0700
0x4060_0900
0x4060_00C0
0x4060_0B00
0x4060_0B80
0x4060_0C00
0x4060_0E00
0x4060_00E0
0x4060_0050
0x4060_0054
0x4060_0058
0x4060_005C
Standard
0x4070_0000
UART
0x4070_0000
0x4070_0000
0x4070_0004
0x4070_0008
0x4070_0008
0x4070_000C
0x4070_0010
0x4070_0014
0x4070_0018
0x4070_001C
0x4070_0020
0x4070_0000
0x4070_0004
Intel® PXA255 Processor Developer's Manual
Register Symbol
UBCR2 UDC Byte Count Register 2
UBCR4 UDC Byte Count Register 4
UBCR7 UDC Byte Count Register 7
UBCR9 UDC Byte Count Register 9
UBCR12 UDC Byte Count Register 12
UBCR14 UDC Byte Count Register 14
UDDR0 UDC Endpoint 0 Data Register
UDDR1 UDC Endpoint 1 Data Register
UDDR2 UDC Endpoint 2 Data Register
UDDR3 UDC Endpoint 3 Data Register
UDDR4 UDC Endpoint 4 Data Register
UDDR5 UDC Endpoint 5 Data Register
UDDR6 UDC Endpoint 6 Data Register
UDDR7 UDC Endpoint 7 Data Register
UDDR8 UDC Endpoint 8 Data Register
UDDR9 UDC Endpoint 9 Data Register
UDDR10 UDC Endpoint 10 Data Register
UDDR11 UDC Endpoint 11 Data Register
UDDR12 UDC Endpoint 12 Data Register
UDDR13 UDC Endpoint 13 Data Register
UDDR14 UDC Endpoint 14 Data Register
UDDR15 UDC Endpoint 15 Data Register
UICR0 UDC Interrupt Control Register 0
UICR1 UDC Interrupt Control Register 1
USIR0 UDC Status Interrupt Register 0
USIR1 UDC Status Interrupt Register 1
STRBR Receive Buffer Register (read only)
STTHR Transmit Holding Register (write only)
STIER Interrupt Enable Register (read/write)
STIIR Interrupt ID Register (read only)
STFCR FIFO Control Register (write only)
STLCR Line Control Register (read/write)
STMCR Modem Control Register (read/write)
STLSR Line Status Register (read only)
STMSR Reserved
STSPR Scratch Pad Register (read/write)
STISR Infrared Selection Register (read/write)
STDLL Divisor Latch Low Register (DLAB = 1) (read/write)
STDLH Divisor Latch High Register (DLAB = 1) (read/write)
System Architecture
Register Description
2-27