Programmable Serial Protocol (Single Transfers); Programmable Serial Protocol (Psp) Parameters - Intel PXA255 Developer's Manual

Network SSP Serial Port
Figure 16-10. Programmable Serial Protocol (single transfers)
(when SCMODE = 0)
(when SCMODE = 1)
(when SCMODE = 2)
(when SCMODE = 3)
(when SFRMP = 1)
(when SFRMP = 0)
Table 16-2. Programmable Serial Protocol (PSP) Parameters
Symbol
—
—
T1
T2
T3
T4
T5
T6
Note: The SSPSFRM delay must not extend beyond the end of T4. SSPSFRM Width must be asserted for
at least 1 SSPSCLK, and must be deasserted before the end of the T4 cycle (i.e. in terms of time,
not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4), 1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1
+ 1) to ensure that SSPSFRM is asserted for at least 2 edges of the SSPSCLK). While the PSP can
be programmed to generate the assertion of SSPSFRM during the middle of the data transfer (after
the MSB was sent), the SSP is not able to receive data in frame slave mode (SSCR1[SFRMDIR] is
16-12
SSPSCLK
SSPSCLK
SSPSCLK
SSPSCLK
SSPTXD Undefined MSB
T1 T2
SSPRXD Undefined
MSB
SSPSFRM
T5 T6
SSPSFRM
Definition
Serial clock mode
(SSPSP[SCMODE])
Serial frame polarity
(SSPSP[SFRMP])
Start delay
(SSPSP[STRTDLY])
Dummy start
(SSPSP[DMYSTRT])
Data size
(SSCR0[EDSS] and SSCR0[DSS])
Dummy stop (SSPSP[DMYSTOP])
SSPSFRM delay (SSPSP[SFRMDLY]
SSPSFRM width (SSPSP[SFRMWDTH]
End of transfer data state (SSPSP[ETDS])
T3
Range
(Drive, Sample, SSPSCLK Idle)
0 - Fall, Rise, Low
1 - Rise, Fall, Low
2 - Rise, Fall, High
3 - Fall, Rise, High
High or Low
0 - 7
0 - 3
4 - 32
0 - 3
0 - 88
1 - 44
Low or [bit 0]
Intel® PXA255 Processor Developer's Manual
End of Transfer
LSB
Data State
T4
Undefined
LSB
A9522-02
Units
—
—
Clock period
Clock period
Clock period
Clock period
Half clock period
Clock period
—