Intel P8700 - Core 2 Duo Processor Datasheet
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Intel P8700 - Core 2 Duo Processor Datasheet

Intel P8700 - Core 2 Duo Processor Datasheet

Core 2 duo mobile processor, intel core 2 solo mobile processor and intel core 2 extreme mobile processor on 45-nm process, platforms based on mobile intel 4 series express chipset family
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Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo
Mobile Processor and Intel® Core™2
Extreme Mobile Processor on 45-nm
Process
Datasheet
For platforms based on Mobile Intel® 4 Series Express Chipset Family
March 2009
Document Number: 320120-004

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Summary of Contents for Intel P8700 - Core 2 Duo Processor

  • Page 1 Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process Datasheet For platforms based on Mobile Intel® 4 Series Express Chipset Family March 2009 Document Number: 320120-004...
  • Page 2 BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel, Pentium, Centrino, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

  • Page 3: Table Of Contents

    FSB Low Power Enhancements ................21 2.4.1 Dynamic FSB Frequency Switching ............21 2.4.2 Enhanced Intel® Dynamic Acceleration Technology ........22 VID-x ......................23 Processor Power Status Indicator (PSI-2) Signal ............ 23 Electrical Specifications ................... 25 Power and Ground Pins ..................25 Decoupling Guidelines ..................
  • Page 4 Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor Package Drawing ........................57 Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA Processor Package Drawing ........................58 Processor Pinout (Top Package View, Left Side) ............59 Processor Pinout (Top Package View, Right Side) ............60...
  • Page 5 Pin Name Listing ...................... 61 Pin # Listing......................72 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name ......84 Signal Description ....................93 Power Specifications for the Dual-Core Extreme Edition Processor......... 101 Power Specifications for the Dual-Core Standard Voltage Processor....... 102 Power Specifications for the Dual-Core Low Power Standard Voltage Processors (25 W) in Standard Package ....................
  • Page 6 — Added Table 23 — Added Table 24 — Added Table 25 • Added information for Intel Core 2 Duo T9800, T9550, P9600, 320120 -003 January 2009 P8700 • Added information for Intel Core 2 Duo processor skus below: — Updated Table 7 and 21 with T9900 —...

  • Page 7: Introduction

    Notes: In this document 1. Intel Core 2 Duo processor, and the Intel Core 2 Extreme processor are referred to as the processor 2. Intel Core 2 Duo LV/ULV/POP processors are referred to as SFF processor 3. Mobile Intel 4 Series Express Chipset is referred as the GMCH.

  • Page 8: Terminology

    • Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies only • Execute Disable Bit support for enhanced security • Intel® Deep Power Down low-power state with P_LVL6 I/O support • Support for Intel® Trusted Execution Technology • Half ratio support (N/2) for core to bus ratio...

  • Page 9: References

    This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.
  • Page 10 Introduction Document Document Number Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669 NOTE: Contact your Intel representative for the latest revision of this document. § Datasheet...

  • Page 11: Low Power Features

    The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel® Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states.

  • Page 12: Core Low-Power States

    Low Power Features Figure 1. Core Low-Power States Stop Grant STPCLK# STPCLK# asserted deasserted STPCLK# STPCLK# deasserted asserted STPCLK# deasserted STPCLK# C1/Auto C1/MWAIT asserted Halt Core state HLT instruction break MWAIT(C1) Halt break P_LVL2 or MWAIT(C2) Core State break Core state †...

  • Page 13: Core Low-Power State Descriptions

    LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information.

  • Page 14: Core C1/Mwait Powerdown State

    MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

  • Page 15: Core Deep Power Down Technology (Code Name C6) State

    Low Power Features 2.1.1.7 Core Deep Power Down Technology (Code Name C6) State Deep Power Down Technology state is a new, power-saving state which is being implemented on the processor. In Deep Power Down Technology the processor saves its entire architectural state onto an on-die SRAM hence allowing it to lower its main core voltage to any value, even as low as 0-V.

  • Page 16: Stop-Grant Snoop State

    Low Power Features 2.1.2.3 Stop-Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.

  • Page 17: Deeper Sleep State

    DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely shut down.
  • Page 18 L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep Power Down Technology state (C6) is enabled (as specified in Section 2.1.1.6).

  • Page 19: Enhanced Intel Speedstep® Technology

    • Enhanced thermal management features: — Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in case of unsuccessful TM2 transition. — Dual-core thermal management synchronization.

  • Page 20: Extended Low-Power States

    Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant and Deeper Sleep states.

  • Page 21: Fsb Low Power Enhancements

    Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor operating frequency from the Enhanced Intel SpeedStep Technology performance states and achieve the Super Low Frequency Mode (Super LFM). This feature is supported at FSB frequencies of 1066 MHz, 800 MHz and 667 MHz and does not entail a change in the external bus signal (BCLK) frequency.

  • Page 22: Enhanced Intel® Dynamic Acceleration Technology

    Intel Dynamic Acceleration Technology mode. Normally, the processor would exit Intel Dynamic Acceleration Technology as soon as two cores are active. This can become an issue if the idle core is frequently awakened for a short periods (i.e., high timer tick rates).

  • Page 23: Vid-X

    Low Power Features When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be active under certain internal conditions. In such a scenario the processor may draw a Instantaneous current (I for a short duration of t ;...
  • Page 24 Low Power Features Datasheet...

  • Page 25: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of V (power) and V (ground) inputs. All power pins must be connected to V power planes while all V pins must be connected to system ground planes.

  • Page 26: Voltage Identification And Power Sequencing

    Electrical Specifications Voltage Identification and Power Sequencing The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0].
  • Page 27 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 2 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000...
  • Page 28 Electrical Specifications Table 2. Voltage Identification Definition (Sheet 3 of 3) VID6 VID5 VID4 VID3 VID2 VID1 VID0 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125...

  • Page 29: Catastrophic Thermal Protection

    Electrical Specifications Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor.

  • Page 30: Fsb Signal Groups

    Electrical Specifications FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

  • Page 31: Cmos Signals

    Electrical Specifications Refer to Chapter 4 for signal descriptions and termination requirements. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

  • Page 32: Processor Dc Specifications

    This rating applies to the processor and does not include any tray or packaging. Failure to adhere to this specification can affect the long-term reliability of the processor. For Intel® Core™2 Duo mobile processors in 22x22 mm package. 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise.
  • Page 33 V and V are high. CC_CORE The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. ™ The I (max) specification of 60 A is for Intel® Core 2 Extreme processors only.

  • Page 34: Voltage And Current Specifications For The Dual-Core, Standard-Voltage Processors

    PLL Supply Voltage 1.425 1.575 at Deeper Sleep 0.65 — 0.85 1, 2 CCDPRSLP at Intel® Enhanced Deeper Sleep State — 0.85 1, 2 at Deep Power Down Technology State (C6) 0.35 — 1, 2 CCDPPWDN for Processors Recommended Design Target —...

  • Page 35: Voltage And Current Specifications For The Dual-Core, Low-Power Standard-Voltage Processors (25 W) In Standard Package

    Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current I of 57 A has to be sustained for short time (t ) of 35 µs.
  • Page 36 Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current I of 49 A has to be sustained for short time (t ) of 35 µs.

  • Page 37: Voltage And Current Specifications For The Dual-Core, Power Optimized Performance (25 W) Sff Processors

    PLL Supply Voltage 1.425 1.575 at Deeper Sleep 0.65 — 0.85 1, 2 CCDPRSLP at Intel® Enhanced Deeper Sleep State — 0.85 1, 2 at Deep Power Down Technology State (C6) 0.35 — 1, 2 CCDPPWDN for Processors Recommended Design Target —...

  • Page 38: Voltage And Current Specifications For The Dual-Core, Low-Voltage Sff Processor

    Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current I of 44 A has to be sustained for short time (t ) of 35 µs.
  • Page 39 Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current I of 36 A has to be sustained for short time (t ) of 35 µs.

  • Page 40: Voltage And Current Specifications For The Dual-Core, Ultra-Low-Voltage Sff Processor

    1.10 PLL Supply Voltage 1.425 1.575 at Deeper Sleep 0.65 — 1, 2 CCDPRSLP at Intel® Enhanced Deeper Sleep State — 1, 2 at Deep Power Down Technology State (C6) 0.35 — 1, 2 CCDPPWDN for Processors Recommended Design Target —...

  • Page 41: Voltage And Current Specifications For The Ultra-Low-Voltage, Single-Core (5.5 W) Sff Processor

    Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Instantaneous current I of 24 A has to be sustained for short time (t ) of 35µs.
  • Page 42 CC_CORE Processor I requirements in Intel Dynamic Acceleration Technology mode are lesser than I in HFM The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or equal to 300 mV. Datasheet...

  • Page 43: Active Vcc And Icc Loadline For Standard Voltage, Low-Power Sv (25 W) And Dual-Core, Extreme Edition Processors

    Electrical Specifications Figure 4. Active V and I Loadline for Standard Voltage, Low-Power SV (25 W) and Dual-Core, Extreme Edition Processors CC-CORE Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. max {HFM|LFM} CC-CORE max {HFM|LFM} CC-CORE, DC 10mV= RIPPLE nom {HFM|LFM}...

  • Page 44: Deeper Sleep Vcc And Icc Loadline For Standard-Voltage, Low-Power Sv (25 W) And Dual-Core Extreme Edition Processors

    Electrical Specifications Figure 5. Deeper Sleep V and I Loadline for Standard-Voltage, Low-Power SV (25 W) and Dual-Core Extreme Edition Processors CC-CORE Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. max {HFM|LFM} CC-CORE max {HFM|LFM} 13mV= RIPPLE CC-CORE, DC nom {HFM|LFM}...

  • Page 45: Deeper Sleep Vcc And Icc Loadline For Low-Power Standard-Voltage Processors

    Electrical Specifications Figure 6. Deeper Sleep V and I Loadline for Low-Power Standard-Voltage Processors CC-CORE Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. max {HFM|LFM} CC-CORE max {HFM|LFM} 10mV= RIPPLE CC-CORE, DC CC-CORE {HFM|LFM} CC-CORE, DC {HFM|LFM} +/-V Tolerance...

  • Page 46: Active Vcc And Icc Loadline For Low-Voltage, Ultra-Low-Voltage And Power Optimized Performance Processor

    Electrical Specifications Figure 7. Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor CC-CORE Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. max {HFM|LFM} CC-CORE max {HFM|LFM} 10mV= RIPPLE CC-CORE, DC nom {HFM|LFM} CC-CORE min {HFM|LFM}...

  • Page 47: Deeper Sleep Vcc And Icc Loadline For Low-Voltage, Ultra-Low-Voltage And Power Optimized Performance Processor

    Electrical Specifications Figure 8. Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized Performance Processor CC-CORE Slope = -4.0 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. max {HFM|LFM} CC-CORE max {HFM|LFM} 10mV= RIPPLE CC-CORE, DC CC-CORE {HFM|LFM} CC-CORE, DC...

  • Page 48: Agtl+ Signal Group Dc Specifications

    Electrical Specifications Table 13. AGTL+ Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 GTLREF Reference Voltage 0.65 0.70 0.72 Compensation Resistor 27.23 27.5 27.78 Ω COMP Termination Resistor Address Ω 11, 12 ODT/A Termination Resistor Data Ω...

  • Page 49: Cmos Signal Group Dc Specifications

    Electrical Specifications Table 14. CMOS Signal Group DC Specifications Symbol Parameter Unit Notes I/O Voltage 1.00 1.05 1.10 Input Low Voltage CMOS -0.10 0.00 0.3*V Input High Voltage 0.7*V +0.1 Output Low Voltage -0.10 0.1*V Output High Voltage 0.9*V +0.1 Output Low Current —...
  • Page 50 Electrical Specifications Datasheet...

  • Page 51: Package Mechanical Specifications And Pin Information

    Package Mechanical Specifications and Pin Information Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor (XE and SV) is available in 478-pin Micro-FCPGA packages as well as 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 9 through Figure The processor (POP, LV, ULV DC and ULV SC) is available 956-ball Micro-FCBGA...

  • Page 52: 6-Mb And 3-Mb On 6-Mb Die Micro-Fcpga Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 9. 6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 53: 10 3-Mb Die Micro-Fcpga Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 10. 3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 54: 11 3-Mb Die Micro-Fcpga Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 11. 3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 55: 12 3-Mb Die Micro-Fcbga Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications and Pin Information Figure 12. 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 56: 13 3-Mb Die Micro-Fcbga Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications and Pin Information Figure 13. 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 57: Intel Core 2 Duo Mobile Processor (Pop And Lv) Die Micro-Fcbga Processor Package Drawing

    Package Mechanical Specifications and Pin Information Figure 14. Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor Package Drawing Datasheet...

  • Page 58: Intel Core 2 Duo Mobile Processor (Ulv Sc And Ulv Dc) Die Micro-Fcbga Processor Package Drawing

    Package Mechanical Specifications and Pin Information Figure 15. Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA Processor Package Drawing Datasheet...

  • Page 59: Processor Pinout And Pin List

    Package Mechanical Specifications and Pin Information Processor Pinout and Pin List Figure 16 Figure 17 show the processor (SV and XE) pinout as viewed from the top of the package. Table 16 provides the pin list, arranged numerically by pin number. Figure 16 through Figure 18...

  • Page 60: Processor Pinout (Top Package View, Right Side)

    Package Mechanical Specifications and Pin Information Figure 17. Processor Pinout (Top Package View, Right Side) BCLK[1] BCLK[0] THRMDA TEST6 BSEL[0] BSEL[1] THRMDC VCCA DBR# BSEL[2] TEST1 TEST3 VCCA PROCHOT IERR# RSVD DPWR# TEST2 D[0]# D[7]# D[6]# D[2]# DRDY# D[4]# D[1]# D[13]# VCCP D[3]#...

  • Page 61: Pin Name Listing

    Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Source Input/ Source Input/ A[24]# A[3]# Synch Output Synch Output Source...
  • Page 62 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Common Source Input/ BPRI# Input D[14]# Clock Synch Output Common Input/...
  • Page 63 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Source Input/ Source Input/ D[36]# D[58]# AE21 Synch Output Synch Output...
  • Page 64 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Source Input/ Common DSTBP[2]# AA26 RS[1]# Input Synch Output Clock Source...
  • Page 65 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AB15 Other Other Power/ Power/ AB17 Other Other Power/...
  • Page 66 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AE12 Other Other Power/ Power/ AE13 Other Other Power/...
  • Page 67 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ VCCP Other Other Power/ Power/ VCCP Other Other Power/...
  • Page 68 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AC14 Other Other Power/ Power/ AC16 Other Other Power/...
  • Page 69 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ AE26 Other Other Power/ Power/ Other Other Power/ Power/...
  • Page 70 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ Other Other Power/ Power/ Other Other Power/ Power/ Other...
  • Page 71 Package Mechanical Specifications and Pin Information Table 16. Pin Name Listing Table 16. Pin Name Listing Signal Signal Pin Name Pin # Buffer Direction Pin Name Pin # Buffer Direction Type Type Power/ Power/ Other Other Power/ Power/ Other Other Power/ Power/ VSSSENSE...

  • Page 72: Pin # Listing

    Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type AA13 Power/Other Power/Other AA14 Power/Other SMI# CMOS Input AA15 Power/Other Power/Other...
  • Page 73 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type Input/ BPM[1]# Common Clock Output AB22 D[51]# Source Synch Output Input/ BPM[0]#...
  • Page 74 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type AE13 Power/Other Input/ AF22 D[62]# Source Synch Output AE14 Power/Other Input/...
  • Page 75 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type Power/Other PROCHOT Input/ Open Drain Output Power/Other RSVD Reserved Power/Other Power/Other...
  • Page 76 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type Power/Other Input/ D[5]# Source Synch Output RS[0]# Common Clock Input Power/Other RS[1]#...
  • Page 77 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type Input/ Power/Other REQ[0]# Source Synch Output Input/ D[23]# Source Synch Power/Other Output...
  • Page 78 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Table 17. Pin # Listing Signal Buffer Directi Signal Buffer Directi Pin # Pin Name Pin # Pin Name Type Type Input/ Input/ D[18]# Source Synch A[18]# Source Synch Output Output Input/...
  • Page 79 Package Mechanical Specifications and Pin Information Table 17. Pin # Listing Signal Buffer Directi Pin # Pin Name Type Input/ D[43]# Source Synch Output Input/ D[44]# Source Synch Output Power/Other Input/ COMP[3] Power/Other Output Input/ A[17]# Source Synch Output Power/Other Input/ A[29]# Source Synch...

  • Page 80: Intel Core 2 Duo Mobile Processor In Sff Package Top View Upper Left Side

    Package Mechanical Specifications and Pin Information Figure 18. Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side COMP[ A[35]# A[17]# A[31]# A[30]# A[19]# A[16]# BPM[3] COMP[ PREQ# A[22]# A[34]# A[32]# A[21]# A[23]# A[11]# VID[5] VID[6]...

  • Page 81: Intel Core 2 Duo Mobile Processor In Sff Package Top View Upper Right Side

    Package Mechanical Specifications and Pin Information Figure 19. Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side AB AA REQ[2] REQ[0] A[7]# A[5]# LOCK# TRDY# DBSY# RSVD0 RSVD0 A[15]# A[9]# A[3]# BR0# RS[0]# HIT# HITM#...

  • Page 82: Intel Core 2 Duo Mobile Processor In Sff Package Top View Lower Left Side

    Package Mechanical Specifications and Pin Information Figure 20. Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side BD BC BB BA AY AW AV AU AR AP AN AM AL AH AG AF AE AD AC...

  • Page 83: Intel Core 2 Duo Mobile Processor In Sff Package Top View Lower Right Side

    Package Mechanical Specifications and Pin Information Figure 21. Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA BCLK[ BCLK[ VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP...

  • Page 84: Intel Core 2 Duo Mobile Processor In Sff Package Listing By Ball Name

    Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number A[3]# BCLK[0] D[20]# A[4]# BCLK[1] D[21]# A[5]# BNR#...
  • Page 85 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number D[56]# AY36 PRDY# AV10 D[57]# AT40 PREQ# TRDY#...
  • Page 86 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number AH22 AP32 AH24 AR33 AH26 AT14 AH28 AT16...
  • Page 87 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number VCCA VCCA VCCP VCCP VCCP VCCP VCCP AA11...
  • Page 88 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number VCCP AG13 VCCP VCCP VCCP AG35 VCCP VCCP...
  • Page 89 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number VCCSENSE BD12 AB42 AG17 VID[0] AG19 VID[1] AC15...
  • Page 90 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number AL23 AR29 AW13 AL25 AR31 AW15 AL27 AR35...
  • Page 91 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number BA33 BA39 BA43 BB12 BB36 BB42 BC11 BC15...
  • Page 92 Package Mechanical Specifications and Pin Information Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name Signal Ball Ball Signal Ball Signal Name Name Number Number Name Number VSSSENSE BC13 Datasheet...

  • Page 93: Alphabetical Signals Reference

    Package Mechanical Specifications and Pin Information Alphabetical Signals Reference Table 19. Signal Description (Sheet 1 of 8) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction.
  • Page 94 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 2 of 8) Name Type Description BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes BPRI# Input...
  • Page 95 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 3 of 8) Name Type Description DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is DEFER# Input normally the responsibility of the addressed memory or input/ output agent.
  • Page 96 For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction application note.
  • Page 97 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 5 of 8) Name Type Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration.
  • Page 98 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 6 of 8) Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies PWRGOOD...
  • Page 99 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop- Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
  • Page 100 Package Mechanical Specifications and Pin Information Table 19. Signal Description (Sheet 8 of 8) Name Type Description VCCSENSE together with VSSSENSE are voltage feedback signals VCCSENSE Output that control the 2.1 mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise.

  • Page 101: Thermal Specifications And Design Considerations

    As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 102: Power Specifications For The Dual-Core Standard Voltage Processor

    As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 103: Power Specifications For The Dual-Core Low Power Standard Voltage Processors (25W) In Standard Package

    As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 104: Power Specifications For The Dual-Core Power Optimized Performance (25 W) Sff

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 105: Power Specifications Fro The Dual-Core Low Voltage (Lv) Sff Processors

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 106: Power Specifications For The Dual-Core Ultra-Low-Voltage (Ulv) Processors

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 107: Power Specifications For The Single-Core Ultra-Low-Voltage (5.5 W) Sff Processors

    Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached.

  • Page 108: Monitoring Die Temperature

    • Digital Thermal Sensor 5.1.1 Thermal Diode Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current characteristics of a substrate PNP transistor. Since these characteristics are a function of temperature, these parameters can be used to calculate silicon temperature values.

  • Page 109: Intel® Thermal Monitor

    Series Resistance Ω NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Characterized across a temperature range of 50-105°C. Not 100% tested. Specified by design characterization. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as...
  • Page 110 Enhanced Intel SpeedStep Technology target frequency point. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature.

  • Page 111: Digital Thermal Sensor

    ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

  • Page 112: Out Of Specification Detection

    Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
  • Page 113 Thermal Specifications and Design Considerations of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. § Datasheet...

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