Udc Endpoint X Control/Status Register (Udccs1/6/11); Udccs1/6/11 Bit Definitions - Intel PXA255 Developer's Manual

12.6.3.8 Setup Active (SA)
The Setup Active bit indicates that the current packet in the FIFO is part of a USB setup command.
This bit generates an interrupt and becomes active at the same time as UDCCS0[OPR]. Software
must clear this bit by writing a 1 to it. Both UDCS0[OPR] and UDCCS0[SA] must be cleared.
12.6.4

UDC Endpoint x Control/Status Register (UDCCS1/6/11)

UDCCS1/6/11, shown in
IN endpoint).
Table 12-15. UDCCS1/6/11 Bit Definitions
0x 4060_0014
0x 4060_0028
0x 4060_003C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
X X X X X X X
Bit Name
31:8
7
6
5
4
3 TUR
2
1
0
12.6.4.1 Transmit FIFO Service (TFS)
The transmit FIFO service bit is active if one or fewer data packets remain in the transmit FIFO.
TFS is cleared when two complete packets of data remain in the FIFO. A complete packet of data is
signified by loading 64 bytes of data or by setting UDCCSx[TSP].
Intel® PXA255 Processor Developer's Manual
Table 12-15, contains 6 bits that are used to operate endpoint(x), a Bulk
reserved
X X X X X X X
— reserved
Transmit short packet
TSP
1 = Short packet ready for transmission.
— reserved
Force STALL
FST
1 = Issue STALL handshakes to IN tokens.
Sent STALL
SST
1 = STALL handshake was sent.
Transmit FIFO underrun
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO
FTF
1 = Flush Contents of TX FIFO
Transmit packet complete
TPC
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service
TFS
0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet
UDCCS1
UDCCS6
UDCCS11
X X X X X X X X X
Description
USB Device Controller
USB Device Controller
8 7 6 5 4 3 2 1
X 0 0 0 0 0 0 0
12-27
0
1