Gplr1 Bit Definitions; Gplr2 Bit Definitions - Intel PXA255 Developer's Manual

System Integration Unit
Table 4-4. GPLR1 Bit Definitions
Physical Address
0x40E0_0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0
Bits Name
<31:0>
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 4-5. GPLR2 Bit Definitions
Physical Address
0x40E0_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0
Bits Name
<31:21>
<20:0>
4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
GPDR0, GPDR1, GPDR2, shown in
an input or an output. The GPDR contain one direction control bit for each of the 85 GPIO pins. If
a direction bit is programmed to a one, the GPIO is an output. If it is programmed to a zero, it is an
input. Reserved bits must be written to zeros and reads to the reserved bits must be ignored.
Note: A reset clears all bits in the GPDR0-2 registers and configures all GPIO pins as inputs.
4-8
0 0 0 0 0 0 0 0
GPIO Pin Level 'x' (where x = 32 to 63).
This read-only field indicates the current value of each GPIO.
PL[x]
0 – Pin state is low
1 – Pin state is high
0 0 0 0 0 0 0 0
— reserved
GPIO Pin Level 'x' (where x = 64 to 84).
This read-only field indicates the current value of each GPIO.
PL[x]
0 – Pin state is low
1 – Pin state is high
GPLR1
0 0 0 0 0 0 0 0
Description
GPLR2
0 0 0 0 0 0 0 0
Description
Table 4-6, Table 4-7, and
Intel® PXA255 Processor Developer's Manual
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
Table 4-8, control whether a pin is
2 1 0
0 0 0
2 1 0
0 0 0