Intel PXA255 Developer's Manual page 17

3-26 Clocks Manager Register Summary ........................................................................................3-41
3-27 Power Manager Register Summary.........................................................................................3-42
4-1 GPIO Alternate Functions..........................................................................................................4-3
4-2 GPIO Register Definitions..........................................................................................................4-6
4-3 GPLR0 Bit Definitions ................................................................................................................4-7
4-4 GPLR1 Bit Definitions ................................................................................................................4-8
4-5 GPLR2 Bit Definitions ................................................................................................................4-8
4-6 GPDR0 Bit Definitions ...............................................................................................................4-9
4-7 GPDR1 Bit Definitions ...............................................................................................................4-9
4-8 GPDR2 Bit Definitions ...............................................................................................................4-9
4-9 GPSR0 Bit Definitions..............................................................................................................4-10
4-10 GPSR1 Bit Definitions..............................................................................................................4-10
4-11 GPSR2 Bit Definitions..............................................................................................................4-11
4-12 GPCR0 Bit Definitions .............................................................................................................4-11
4-13 GPCR1 Bit Definitions .............................................................................................................4-11
4-14 GPCR2 Bit Definitions .............................................................................................................4-12
4-15 GRER0 Bit Definitions .............................................................................................................4-13
4-16 GRER1 Bit Definitions .............................................................................................................4-13
4-17 GRER2 Bit Definitions .............................................................................................................4-13
4-18 GFER0 Bit Definitions..............................................................................................................4-14
4-19 GFER1 Bit Definitions..............................................................................................................4-14
4-20 GFER2 Bit Definitions..............................................................................................................4-14
4-21 GEDR0 Bit Definitions .............................................................................................................4-15
4-22 GEDR1 Bit Definitions .............................................................................................................4-15
4-23 GEDR2 Bit Definitions .............................................................................................................4-16
4-24 GAFR0_L Bit Definitions..........................................................................................................4-17
4-25 GAFR0_U Bit Definitions .........................................................................................................4-17
4-26 GAFR1_L Bit Definitions..........................................................................................................4-18
4-27 GAFR1_U Bit Definitions .........................................................................................................4-18
4-28 GAFR2_L Bit Definitions..........................................................................................................4-19
4-29 GAFR2_U Bit Definitions .........................................................................................................4-19
4-30 ICMR Bit Definitions.................................................................................................................4-22
4-31 ICLR Bit Definitions..................................................................................................................4-23
4-32 ICCR Bit Definitions .................................................................................................................4-23
4-33 ICIP Bit Definitions...................................................................................................................4-24
4-34 ICFP Bit Definitions..................................................................................................................4-24
4-35 ICPR Bit Definitions .................................................................................................................4-25
4-36 List of First-Level Interrupts ....................................................................................................4-27
4-37 RTTR Bit Definitions ................................................................................................................4-30
4-38 RTAR Bit Definitions ................................................................................................................4-30
4-39 RCNR Bit Definitions ...............................................................................................................4-31
4-40 RTSR Bit Definitions ................................................................................................................4-32
4-41 OSMR[x] Bit Definitions ...........................................................................................................4-36
4-42 OIER Bit Definitions .................................................................................................................4-36
4-43 OWER Bit Definitions...............................................................................................................4-37
4-44 OSCR Bit Definitions ...............................................................................................................4-37
4-45 OSSR Bit Definitions................................................................................................................4-38
4-46 PWM_CTRLn Bit Definitions....................................................................................................4-41
4-47 PWM_DUTYn Bit Definitions ...................................................................................................4-42
4-48 PWM_PERVALn Bit Definitions...............................................................................................4-43
Intel® PXA255 Processor Developer's Manual
Contents
xvii