Power Manager Falling-Edge Detect Enable Register (Pfer); Pfer Bit Definitions - Intel PXA255 Developer's Manual

3.5.5 Power Manager Falling-Edge Detect Enable Register
(PFER)
The PFER,
sleep mode on that GPIO pin's falling edge. When PWER[IDAE] is zero and a fault condition is
detected on the nVDD_FAULT or nBATT_FAULT pin, PFER is set to 0x0000_0003. This enables
falling edges on GP[1:0] to act as wake up sources. When PWER[IDAE] is set, fault conditions on
the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PFER is also set to
0x0000_0003 during hardware, watchdog, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-11. PFER Bit Definitions
0x40F0_0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0
Bits
[31:16]
[15:0]
Intel® PXA255 Processor Developer's Manual
Table 3-11, determines if the GPIO pin enabled with the PWER causes a wake up from
0 0 0 0 0 0 0 0
Name
Reserved.
—
Read undefined and must always be written with zeroes.
Sleep mode Falling-edge Wake-up Enable
0 – Wake up due to GPx falling-edge detect disabled.
FEx
1 – Wake up due to GPx falling-edge detect enabled.
Set to 0x0003 on hardware, watchdog, and GPIO resets.
PFER
0 0 0 0 0 0 0 0
Description
Clocks and Power Manager
Clocks and Power Manager
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 1 1
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