Scratchpad Register (Scr); Infrared Selection Register (Isr); Scr Bit Definitions - Intel PXA255 Developer's Manual

Hardware UART
Table 17-17. MSR Bit Definitions (Sheet 2 of 2)
Physical Address
0x4160_0018
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Name
4
3:1
0 DCTS
17.5.14

Scratchpad Register (SCR)

The SCR, shown in
for use by the programmer. It is included for 16550A compatibility.
This is a read-only register. Ignore reads from reserved bits.
Table 17-18. SCR Bit Definitions
Physical Address
0x4160_001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Name
31:8
7:0
17.5.15

Infrared Selection Register (ISR)

Each UART can manage an IrDA module. The ISR, shown in
(see Section
This is a read/write register. Ignore reads to reserved bits. Write zeros to reserved bits.
17-24
Modem Status Register (MSR)
reserved
? ? ? ? ? ? ?
CLEAR TO SEND
Complement of the clear to send (nCTS) input. Equivalent to MCR[RTS] if MCR[LOOP] is
CTS set.
0 = nCTS pin is 1
1 = nCTS pin is 0
— reserved
DELTA CLEAR TO SEND
0 = No change in nCTS pin since last read of MSR
1 = nCTS pin has changed state
Table 17-18, has no effect on the UART. It is intended as a scratchpad register
Scratchpad Register (SCR)
reserved
? ? ? ? ? ? ?
— reserved
SCR No effect on UART function
17.4.5).
? ? ? ? ? ? ? ?
Description
? ? ? ? ? ? ? ?
Description
Intel® PXA255 Processor Developer's Manual
PXA255 Processor Hardware UART
8 7 6 5 4 3
? ? ? ? ? ? 1 ?
PXA255 Processor Hardware UART
8 7 6 5 4 3
SCR
? ? ? 0 0 0 0 0
Table 17-19, controls IrDA functions
2 1 0
? ? 0
2 1 0
0 0 0