Usb Device Controller - Intel PXA255 Developer's Manual

Intel computer hardware user manual

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Table 12-33. USB Device Controller Register Summary (Sheet 2 of 3)

Intel® PXA255 Processor Developer's Manual

UDC Endpoint 0 Control/Status Register

UDC Endpoint 1 (IN) Control/Status Register

UDC Endpoint 2 (OUT) Control/Status Register

UDC Endpoint 3 (IN) Control/Status Register

UDC Endpoint 4 (OUT) Control/Status Register

UDC Endpoint 5 (Interrupt) Control/Status Register

UDC Endpoint 6 (IN) Control/Status Register

UDC Endpoint 7 (OUT) Control/Status Register

UDC Endpoint 8 (IN) Control/Status Register

UDC Endpoint 9 (OUT) Control/Status Register

UDC Endpoint 10 (Interrupt) Control/Status Register

UDC Endpoint 11 (IN) Control/Status Register

UDC Endpoint 12 (OUT) Control/Status Register

UDC Endpoint 13 (IN) Control/Status Register

UDC Endpoint 14 (OUT) Control/Status Register

UDC Endpoint 15 (Interrupt) Control/Status Register

UDC Interrupt Control Register 0

UDC Interrupt Control Register 1

UDC Status Interrupt Register 0

UDC Status Interrupt Register 1

UDC Frame Number Register High

UDC Frame Number Register Low

UDC Byte Count Register 2

UDC Byte Count Register 4

UDC Byte Count Register 7

UDC Byte Count Register 9

UDC Byte Count Register 12

UDC Byte Count Register 14

UDC Endpoint 0 Data Register

UDC Endpoint 1 Data Register

UDC Endpoint 2 Data Register

UDC Endpoint 3 Data Register

UDC Endpoint 4 Data Register

UDC Endpoint 5 Data Register

UDC Endpoint 6 Data Register

UDC Endpoint 7 Data Register

UDC Endpoint 8 Data Register

UDC Endpoint 9 Data Register