Intel PXA255 Developer's Manual page 61

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Table 2-8. System Architecture Register Address Summary (Sheet 11 of 12)

Intel® PXA255 Processor Developer's Manual

NSSP Programmable Serial Protocol

Receive Buffer Register (read only)

Transmit Holding Register (write only)

Interrupt Enable Register (read/write)

Interrupt ID Register (read only)

FIFO Control Register (write only)

Line Control Register (read/write)

Modem Control Register (read/write)

Line Status Register (read only)

Modem Status Register (read only)

Scratch Pad Register (read/write)

Infrared Selection Register (read/write)

FIFO Occupancy Register (read only)

Auto-Baud Control Register (read/write)

Auto-Baud Count Register

Divisor Latch Low Register (DLAB = 1) (read/write)

Divisor Latch High Register (DLAB = 1) (read/write)

LCD Controller Control Register 0

LCD Controller Control Register 1

LCD Controller Control Register 2

LCD Controller Control Register 3

DMA Channel 0 Frame Descriptor Address Register

DMA Channel 0 Frame Source Address Register

DMA Channel 0 Frame ID Register

DMA Channel 0 Command Register

DMA Channel 1 Frame Descriptor Address Register

DMA Channel 1 Frame Source Address Register

DMA Channel 1 Frame ID Register

DMA Channel 1 Command Register

DMA Channel 0 Frame Branch Register

DMA Channel 1 Frame Branch Register

LCD Controller Status Register

LCD Controller Interrupt ID Register

TMED RGB Seed Register

TMED Control Register

System Architecture

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