Dma Controller; Dma Description; Dmac Block Diagram - Intel PXA255 Developer's Manual

DMA Controller

This chapter describes the on-chip DMA controller (DMAC) for the PXA255 processor. The
DMAC transfers data to and from main memory in response to requests generated by internal and
external peripherals. The peripherals do not directly supply addresses and commands to the
memory system. The DMAC has 16 DMA channels, 0 through 15, and every DMA request from
the peripheral generates at least one memory bus cycle.
5.1

DMA Description

The DMAC supports only flow-through transfers.
Flow-through data passes through the DMAC before the data is latched by the destination in its
buffers/memory. This DMAC can perform memory-to-memory moves with flow-through transfers.
Figure 5-1
descriptions.
Figure 5-1. DMAC Block Diagram
DREQ[1:0]
(external)
PREQ[37:0]
(internal)
Intel® PXA255 Processor Developer's Manual
provides an overview of the DMAC.
Control Registers
DCSR0
DRCMR0
DINT
Table 5-1 provides a list of the DMAC signals and
Memory Controller
System Bus (internal)
DMA Controller
16 DMA Channels
Channel 15
Channel 0
DDADR0
DSADR0
DTADR0
DCMD0
Peripheral Bus
(internal)
5
DMA_IRQ
(internal)
5-1