Mocr Bit Definitions - Intel PXA255 Developer's Manual

Figure 13-10. Mic-in Receive-Only Operation
0x0000
31
13.8.3.12 Modem-Out Control Register (MOCR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 13-18. MOCR Bit Definitions
Physical Address
4050_0100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:4
3 FEIE
2:0
13.8.3.13 Modem-In Control Register (MICR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
Processor/DMA
Read
MCDR Register
0
16 15
RxFIFO
Read
MOCR Register
reserved
0 0 0 0 0 0 0
— reserved
FIFO Error Interrupt Enable (FEIE)
This bit controls whether the occurrence of a transmit FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the MOSR is set
1 = An interrupt will occur if bit 4 in the MOSR is set.
— reserved
Receive
Data
RxEntry15
Mic-in Receive FIFO
RxEntry3
RxEntry2
RxEntry1
RxEntry0
15
0 0 0 0 0 0 0 0
Description
AC'97 Controller Unit
0
AC'97
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
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