Smrom Boot Time Configurations And Register Defaults - Intel PXA255 Developer's Manual

Figure 6-34. SMROM Boot Time Configurations and Register Defaults
BOOT_SEL[2:0] = 100
32
16
32
16
MRS value must be 0061h.
The number of banks in the device defaults to zero.
BOOT_SEL[2:0] = 101
16
MRS value must be 0061h.
The number of banks in the device defaults to zero.
Intel® PXA255 Processor Developer's Manual
SMROM
MSC0
32-bit
(64 Mbit)
RBW0 = 0
(nWORD = 1)
SXCNFG
or
SXEN0 = 1h, SXCL0 = 4h (CL = 5),
SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),
SMROM
SXCA0 = 1h (8-bits), SXTP0 = 0h, SXLATCH=1h
16-bit
(32 Mbit)
MDREFR
(nWORD = 0)
E0PIN = 1, K0RUN = 1
SMROM
16-bit
BOOT_SEL[2:0] = 100
(32 Mbit)
(nWORD = 0)
BOOT_SEL[2:0] = 101
BOOT_SEL[2:0] = 110
BOOT_SEL[2:0] = 111
MSC0
RBW0 = 1
SMROM
16-bit
(64 Mbit)
SXCNFG
(nWORD = '0')
SXEN0 = 1h, SXCL0 = 4h (CL = 5),
SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),
SXCA0 = 2h (9-bits), SXTP0 = 0h, SXLATCH=1h
MDREFR
E0PIN = 1, K0RUN = 1
7FF0 7FF0
0004 4531
03CA 7FFF
SXMRS 0232 0232
SXMRS
0232 0232
SXMRS 0232 0232
SXMRS
0232 0232
7FF0 7FF8
0004 4931
03CA 7FFF
Memory Controller
6-77