Bit Variable Latency I/O Read Timing (Burst-Of-Four, One Wait Cycle Per Beat) (Msc0[Rdf] = 2, Msc0[Rdn] = 2, Msc0[Rrr] = 1) - Intel PXA255 Developer's Manual

Memory Controller
6.7.6.1 Variable Latency I/O Timing Diagrams and Parameters
Figure 6-21
Variable Latency I/O writes.
Figure 6-21. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)
(MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1)
0ns
CLK_MEM
nCS[0]
MA[25:2]
MA[1:0]
nOE
nPWE
RDnWR
RDY
RDY_sync
MD[31:0]
DQM[3:0]
6-56
shows the timing for Variable Latency I/O reads and
100ns
tAS
addr addr + 1
RDN+2 RDN
0 Waits 1 Wait
*MSC0: RDF0 = 3, RDN0 = 2, RRR0 = 1
Figure 6-22
200ns
addr + 2
"00"
RDN+ RDN+2
2 Waits
RDF+1+Waits RDF+1+Waits RDF+1+Waits RDF+1+Waits
"0000"
tAS = Address Setup to nCS asserted = 1 clk_mem
tAH = Address Hold from nOE deasserted = 1 clk_mem
tASRW0 = Address Setup to nOE asserted (1st access) = 3 clk_mems
tASRWn = Address Setup to nOE asserted (next access(s)) = RDN clk_mems
tCES = nCS setup to nOE asserted = 2 clk_mems
tCEH = nCS hold from nOE deasserted = 1 clk_mem
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns
tRDYH = RDY Hold from nOE deasserted = 0 ns
Intel® PXA255 Processor Developer's Manual
shows the timing for
300ns
addr + 3
RDN+ RDN+2
3 Waits
RDF+1+Waits RDF+1+Waits RRR*2+1