Intel PXA255 Developer's Manual page 598

Hardware UART
Table 17-20. HWUART Register Locations (Sheet 2 of 2)
Register
Addresses
0x4160_0008
0x4160_0008
0x4160_000C
0x4160_0010
0x4160_0014
0x4160_0018
0x4160_001C
0x4160_0020
0x4160_0024
0x4160_0028
0x4160_002C
0x4160_0000
0x4160_0004
17-26
DLAB Bit
Name
Value
X HWIIR "Interrupt Identification Register (IIR)"
X HWFCR "FIFO Control Register (FCR)"
X HWLCR "Line Control Register (LCR)"
X HWMCR "Modem Control Register (MCR)"
X HWLSR "Line Status Register (LSR)"
X HWMSR "Modem Status Register (MSR)"
X HWSPR "Scratchpad Register (SCR)"
X HWISR "Infrared Selection Register (ISR)"
X HWFOR "Receive FIFO Occupancy Register (FOR)"
X HWABR "Auto-Baud Control Register (ABR)"
X HWACR "Auto-Baud Count Register (ACR)"
1 HWDLL "Divisor Latch Registers (DLL and DLH)"
1 HWDLH "Divisor Latch Registers (DLL and DLH)"
Description
(write only)
(read/write)
(read/write)
(read only)
(read only)
(read/write)
(read/write)
(read/write)
Intel® PXA255 Processor Developer's Manual
(read only)
(read only)
low byte (read/write)
high byte (read/write)