I2C Acknowledge; Data Format Of First Byte In Master Transaction - Intel PXA255 Developer's Manual

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I C Bus Interface Unit
9.4.2.1 Addressing a Slave Device
As a master device, the I
consists of the slave address for the intended device and a R/nW bit for transaction definition. The
MSB is transmitted first. The slave address and the R/nW bit are written to the IDBR (see
Figure 9-4).
Figure 9-4. Data Format of First Byte in Master Transaction
The first byte transmission must be followed by an ACK pulse from the addressed slave. When the
transaction is a write, the I
stays in slave-receive mode. When the transaction is a read, the I
receive mode immediately following the ACK and the addressed slave device transitions to slave-
transmit mode. When a NAK is returned, the I
sending a STOP and setting the ISR[BED] bit.
When the I
for a START signal. When it detects a START pulse, the I
compares them to those in the ISAR and the general call address (0x00). When the bits match those
in the ISAR register, the I
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I C unit either remains in slave-receive mode (R/nW = 0) or transitions to slave-transmit mode (R/
nW = 1). See
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9.4.3 I C Acknowledge
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Every I C byte transfer must be accompanied by an acknowledge pulse that the master- or slave-
receiver must generate. The transmitter must release the SDA line for the receiver to transmit the
acknowledge pulse (see
9-8
2
C unit must compose and send the first byte of a transaction. This byte
Read/Write Transaction
(0) Write
(1) Read
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7-Bit I C Slave Address
2
C unit remains in master-transmit mode and the addressed slave device
2
C unit is enabled and idle, it remains in slave-receive mode and monitors the I
2
C unit reads the eighth bit (R/nW bit) and transmits an ACK pulse. The
Section 9.4.8 for actions when a general call address is detected.
Figure 9-5).
7
0
MSB
LSB
2
C unit transitions to master-
2
C unit aborts the transaction by automatically
2
C unit reads the first seven bits and
Intel® PXA255 Processor Developer's Manual
2
C bus