Intel PXA255 Developer's Manual page 371

Table 10-11. FCR Bit Definitions (Sheet 2 of 2)
Base+0x08
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
2 RESETTF
1 RESETRF
0 TRFIFOE
10.4.2.7 Line Control Register (LCR)
The LCR, shown in
exchange. The serial data format consists of a start bit, five to eight data bits, an optional parity bit,
and one, one and a half, or two stop bits. The LCR has bits that allow access to the Divisor Latch
and bits that can cause a break condition.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
FIFO Control Register
reserved
0 0 0 0 0 0 0 0
Reset transmitter FIFO: When RESETTF is set to 1, all the bytes in the transmitter FIFO
are cleared. The TDRQ bit in the LSR is set and the IIR shows a transmitter requests data
interrupt, if the TIE bit in the IER register is set. The transmitter shift register is not cleared
and it completes the current transmission.
0 – Writing 0 has no effect
1 – The transmitter FIFO is cleared
Reset Receiver FIFO: When RESETRF is set to 1, all the bytes in the receiver FIFO are
cleared. The DR bit in the LSR is reset to 0. All the error bits in the FIFO and the FIFOE bit
in the LSR are cleared. Any error bits, OE, PE, FE or BI, that had been set in LSR are still
set. The receiver shift register is not cleared. If the IIR had been set to Received Data
Available, it is cleared.
0 – Writing 0 has no effect
1 – The receiver FIFO is cleared
Transmit and Receive FIFO Enable: TRFIFOE enables/disables the transmitter and
receiver FIFOs. When TRFIFOE = 1, both FIFOs are enabled (FIFO Mode). When
TRFIFOE = 0, the FIFOs are both disabled (non-FIFO Mode). Writing a 0 to this bit clears
all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice
versa, data is automatically cleared from the FIFOs. This bit must be 1 when other bits in
this register are written or the other bits are not programmed.
0 – FIFOs are disabled
1 – FIFOs are enabled
Table 10-12, specifies the format for the asynchronous data communications
0 0 0 0 0 0 0 0
Description
UARTs
UART
8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
1 0
0 0
10-13