Mmc_Txfifo Fifo; Multimediacard Controller Register Summary; Mmc_Txfifo, Fifo Entry; Mmc Controller Registers - Intel PXA255 Developer's Manual

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MMC_TXFIFO FIFO

MMC_TXFIFO, shown in

wide by 32 entries deep. This FIFO holds the data to be written to a card. It is a write only FIFO to

the software, and is written on boundaries eight bits wide. The eight bits of data are written on a 32-

bit APB and occupy the least significant byte lane (7:0).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 15-23. MMC_TXFIFO, FIFO Entry

Physical Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

WRITE_DATA One byte of write data

Table 15-24. MMC Controller Registers (Sheet 1 of 2)

Intel® PXA255 Processor Developer's Manual

15-23, consists of two dual FIFOs, where each FIFO is eight bits

MMC_TXFIFO Entry

lists the address, name, and description of the MMC Controller Registers.

Control to start and stop MMC clock

MMC status register (read only)

MMC clock rate

SPI mode control bits

Command/response/data sequence control

Expected response time out

Expected data read time out

Block length of data transaction

Number of blocks, for block mode

Partial MMC_TXFIFO FIFO written

Interrupt Mask

Interrupt Register (read only)

Index of current command

MSW part of the current command argument

LSW part of the current command argument

MultiMediaCard Controller

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