Intel PXA255 Developer's Manual page 19

6-33 Attribute Memory Space Write Commands .............................................................................6-65
6-34 Attribute Memory Space Read Commands .............................................................................6-65
6-35 16-Bit I/O Space Write Commands (nIOIS16 = 0) ...................................................................6-65
6-36 16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................6-65
6-37 8-Bit I/O Space Write Commands (nIOIS16 = 1) .....................................................................6-66
6-38 8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-66
6-39 BOOT_SEL Definitions ............................................................................................................6-74
6-40 BOOT_DEF Bitmap .................................................................................................................6-75
6-41 Valid Boot Configurations Based on Processor Type..............................................................6-75
6-42 Memory Controller Pin Reset Values.......................................................................................6-79
6-43 Memory Controller Register Summary ....................................................................................6-81
7-1 Pin Descriptions.........................................................................................................................7-4
7-2 LCD Controller Data Pin Utilization..........................................................................................7-21
7-3 LCCR0 Bit Definitions ..............................................................................................................7-23
7-4 LCCR1 Bit Definitions ..............................................................................................................7-26
7-5 LCCR2 Bit Definitions ..............................................................................................................7-28
7-6 LCCR3 Bit Definitions ..............................................................................................................7-31
7-7 FDADRx Bit Definitions............................................................................................................7-33
7-8 FSADRx Bit Definitions............................................................................................................7-34
7-9 FIDRx Bit Definitions................................................................................................................7-34
7-10 LDCMDx Bit Definitions ...........................................................................................................7-36
7-11 FBRx Bit Definitions.................................................................................................................7-37
7-12 LCSR Bit Definitions ................................................................................................................7-40
7-13 LIICR Bit Definitions.................................................................................................................7-41
7-14 TRGBR Bit Definitions .............................................................................................................7-42
7-15 TCR Bit Definitions ..................................................................................................................7-44
7-16 LCD Controller Register Summary ..........................................................................................7-44
8-1 External Interface to Codec .......................................................................................................8-1
8-2 SSCR0 Bit Definitions................................................................................................................8-9
8-3 SSCR1 Bit Definitions..............................................................................................................8-11
8-4 TFT and RFT Values for DMA Servicing .................................................................................8-15
8-5 SSDR Bit Definitions................................................................................................................8-15
8-6 SSSR Bit Definitions ................................................................................................................8-17
8-7 SSP Controller Register Summary ..........................................................................................8-19
9-1 I2C Signal Description ...............................................................................................................9-1
9-2 I2C Bus Definitions ...................................................................................................................9-2
9-3 Modes of Operation ...................................................................................................................9-3
9-4 START and STOP Bit Definitions ..............................................................................................9-4
9-5 Master Transactions ................................................................................................................9-12
9-6 Slave Transactions ..................................................................................................................9-15
9-7 General Call Address Second Byte Definitions .......................................................................9-17
9-8 IBMR Bit Definitions................................................................................................................9-22
9-9 IDBR Bit Definitions ................................................................................................................9-23
9-10 ICR Bit Definitions...................................................................................................................9-23
9-11 ISR Bit Definitions...................................................................................................................9-26
9-12 ISAR Bit Definitions ................................................................................................................9-27
10-1 UART Signal Descriptions .......................................................................................................10-3
10-2 UART Register Addresses as Offsets of a Base .....................................................................10-6
10-3 RBR Bit Definitions ..................................................................................................................10-6
10-4 THR Bit Definitions ..................................................................................................................10-7
Intel® PXA255 Processor Developer's Manual
Contents
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