Interrupt Identification Register Decode - Intel PXA255 Developer's Manual

Hardware UART
Table 17-8. IIR Bit Definitions (Sheet 2 of 2)
Physical Address
0x4160_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Name
4
3
2:1 IID[1:0]
0
Table 17-9
also gives the reset condition used to deassert the interrupts. Bits (0-3) of the IIR register represent
priority encoded interrupts. Bits (4-7) do not.
Table 17-9. Interrupt Identification Register Decode (Sheet 1 of 2)
Interrupt ID bits
3 2 1 0 Priority
nIP 0 0 0 1 -
IID[11] 0 1 1 0 Highest
Second
IID[10] 0 1 0 0
Highest
Second
TOD 1 1 0 0
Highest
Third
IID[01] 0 0 1 0
Highest
17-14
Interrupt Identification Register
reserved
? ? ? ? ? ? ?
Autobaud Lock (Section 17.4.4
ABL
0 = Autobaud circuitry has not programmed Divisor Latch registers (DLR).
1 = Divisor Latch registers (DLR) programmed by auto-baud circuitry.
Time Out Detected (See
TOD
0 = No time out interrupt is pending
1 = Time out Interrupt is pending. (FIFO mode only)
Interrupt Source Encoded:
00 – Modem status (CTS, DSR, RI, DCD modem signals changed state)
01 – Transmit FIFO requests data
10 – Received data available
11 – Receive error (overrun, parity, framing, break, FIFO error.
See Table 17-17
Interrupt Pending:
nIP
0 = Interrupt is pending. (Active low)
1 = No interrupt is pending
shows the priority, type, and source of the Interrupt Identification register interrupts. It
Type
None No interrupt is pending.
Receiver Line Overrun error, parity error, framing
Status error, break interrupt.
Non-FIFO mode – Receive buffer is
full.
Received Data
FIFO mode – Trigger threshold was
Available.
reached.
Character FIFO mode only: At least 1 character
Timeout is left in the receive buffer indicating
indication. trailing bytes.
Non-FIFO mode: Transmit Holding
register empty
Transmit FIFO
Data Request
FIFO mode: transmit FIFO has half or
less than half data.
(IIR)
? ? ? ? ? ? ? ?
Description
):
Section 17.4.2.1.2, "Character Timeout Interrupt"
)
Interrupt SET/RESET Function
Source
Intel® PXA255 Processor Developer's Manual
PXA255 Processor Hardware UART
8 7 6 5 4 3
? ? ? 0 0 ? 0 0
):
RESET Control
—
Reading the Line Status register.
Non-FIFO mode – Reading the
Receiver Buffer register.
FIFO mode – Reading bytes until
receiver FIFO drops below trigger
threshold or setting RESETRF bit in
FIFO Control register (FCR).
Reading the receiver FIFO or setting
RESETRF bit in FCR.
Reading the IIR (if the source of the
interrupt) or writing into the Transmit
Holding register.
Reading the IIR (if the source of the
interrupt) or writing to the transmitter
FIFO.
2 1 0
0 0 1