Mcatt0/1 Bit Definitions; Mcio0/1 Bit Definitions - Intel PXA255 Developer's Manual

Table 6-27. MCATT0/1 Bit Definitions
0x4800_0030
0x4800_0030
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
31:20
MCATTx_HO
19:14
13:12
MCATTx_AS
11:7
MCATTx_SE
6:0
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 6-28. MCIO0/1 Bit Definitions
0x4800_0038
0x4800_003C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
31:20
MCIOx_HOL
19:14
13:12
MCIOx_ASS
11:7
6:0 MCIOx_SET
Intel® PXA255 Processor Developer's Manual
0 0 0 0 0 0 0
— reserved
Minimum Number of memory clocks to set up address before command assertion for
LD MCATT for socket x is equal to MCATTx_HOLD + 2.
— reserved
Code for the command assertion time. See
ST affects on the command assertion.
Minimum Number of memory clocks to set up address before command assertion for
T MCATT for socket x is equal to MCATTx_SET + 2.
0 0 0 0 0 0 0
— reserved
Minimum Number of memory clocks to set up address before command assertion for MCIO
D for socket x is equal to MCIOx_HOLD + 2.
— reserved
Code for the command assertion time. See
T affects on the command assertion.
Minimum Number of memory clocks to set up address before command assertion for MCIO
for socket x is equal to MCIOx_SET + 2.
MCATT0
MCATT1
ATTx_HOLD
0 0 0 0 0 0 0 0
Description
Table 6-29
MCIO0
MCIO1
IOx_HOLD
0 0 0 0 0 0 0 0
Description
Table 6-29
Memory Controller
Memory Controller
8 7 6 5 4 3
ATTx_SET
ATTx_ASST
0 0 0 0 0 0 0 0
for a description of this code and its
Memory Controller
8 7 6 5 4 3
IOx_ASST IOx_SET
0 0 0 0 0 0 0 0
for a description of this code and its
2 1 0
0 0 0
2 1 0
0 0 0
6-61