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Intel PXA27x Series Specification Update
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Intel PXA27x Series Specification Update

Intel PXA27x Series Specification Update

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Download this manual See also: User Manual
Intel® PXA27x Processor Family
Specification Update
October 2004
.Notice: The Intel® PXA27x Processor Family may contain design defects or errors known as
errata that may cause the product to deviate from published specifications. Current characterized
errata are documented in this specification update.
Order Number:
280071-003

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Summary of Contents for Intel PXA27x Series

  • Page 1 Intel® PXA27x Processor Family Specification Update October 2004 .Notice: The Intel® PXA27x Processor Family may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
  • Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com.

  • Page 3: Revision History

    Revision History Revision Date Version October, 2004 August, 2004 April, 2004 Intel® PXA27x Processor Family Specification Update Description Added Errata 51, 52, 53, Added Errata 48, 49, Added Documentation Changes First publication Revision History...
  • Page 4 Preface Preface This document contains updates to the specifications for the Intel® PXA27x Processor Family, listed in Table 1. This document is a compilation of device and documentation errata, specification clarifications, and specification changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, and tools.
  • Page 5 Affected and Related Documents Table 1 lists the documents affected by and related to this errata update. Contact an Intel® representative to obtain the latest revisions of these documents. Table 1. Affected Documents / Related Documents Title Intel® PXA27x Processor Family Developer’s Manual Intel®...
  • Page 6 Nomenclature Nomenclature Errata are design defects or errors. These errata might cause the Intel® PXA27x Processor Family’s behavior to deviate from published specifications. Hardware and software designed to be used with any given processor stepping must assume that all errata documented for that stepping are present on all devices unless otherwise noted.
  • Page 7 Intel® PXA27x Processor Family Package Markings The following figure depicts the location, on specific Intel® PXA27x Processor Family packages, where the actual markings are located. Actual markings are described in Figure 1.Intel® PXA27x Processor Family Package Markings Locations Table 2 describes the actual markings that are on the package at the location indicated by “LINE x”...
  • Page 8 Intel® PXA27x Processor Family Package Markings Note: This table is for example only. It must not be used to determine final production offerings. Table 2. Example Processor Package Markings (For Example Only) Discrete/ 13x13 T-PBGA Max. 624 MHz Freq. Lead/...

  • Page 9: Summary Of Changes

    The following tables summarize the errata, specification changes, specification clarifications, and documentation changes that apply to the Intel® PXA27x Processor Family. Intel might fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted.
  • Page 10 CORE: Non-branch instruction in vector table may execute twice after a thumb mode exception UART: UART does not correctly indicate a Framing Error Interrupt in DMA mode. References Intel® PXA27x Processor Family Specification Update Status Page No Fix No Fix...
  • Page 11 NOTE: There are no specification changes at this time. Table 5. Summary of Specification Clarifications Number Document Revision NOTE: There are no specification clarifications at this time. Intel® PXA27x Processor Family Specification Update References References Page Status Summary of Changes...
  • Page 12 Summary of Changes Table 6. Summary of Documentation Changes Number Document Revision Page Status Documentation Changes NOTE: There are no documentation changes at this time. Intel® PXA27x Processor Family Specification Update...
  • Page 13 2. Another master externally modifies address A 3. An Intel XScale® core store instruction attempts to modify A, hits the cache, aborts because of MMU permissions, and is backed out the of cache. That line should not be marked “dirty”, but because of this defect it will be.
  • Page 14 This problem affects only processors that use the core’s trace interface. An I-cache or I-TLB lock Problem: operation that results in lock abort creates a unique internal pipeline signal timing that causes Intel® PXA27x Processor Family Specification Update...
  • Page 15 0, r0, c1, c0, 0 p15, 0, r0, c2, c0, 0 r0, r0 pc, pc, #4 Status: No Fix Intel® PXA27x Processor Family Specification Update ;// @ unlock I-TLB ;//@ invalidate I-TLB ;//@ CPWAIT ;//@ branch to aligned code ;//@ align to 32 bytes ;//@ enable/disable MMU, caches...
  • Page 16 The first vector to the ISR occurs on first key down. The second vector is unexpected. This is possibly caused by the second key down. The third vector occurs approximately at the time of all keys up. Debounce interval = 3ms, KPC[IMKP] = 1, KPC[ASACT] = 0; KPC[MI] = 1. Intel® PXA27x Processor Family Specification Update...

  • Page 17: Current Consumption

    The following describes the current consumption in order of voltage domain bootup sequence. • If the voltage rise/stabilization time of VCC_BATT is longer than 500µsec at room temperature, then the combined current on VCC_BATT will be less than 100mA for less than 20µsec. Intel® PXA27x Processor Family Specification Update Errata...
  • Page 18 The test is trying to put the memory stick to ”SLEEP” and then wake it up by sending the “RESET” Problem: TPC. The manual says that “Memory Stick wakes up and performs a packet processing, when a packet transfer by SET_CMD TPC or Write_Reg occurs at SL = 1 in Status Register 0”. Intel® PXA27x Processor Family Specification Update...
  • Page 19 9. Updating the overlay/cursor registers if required. Follow the instructions mentioned in the manual in section 7.4.7 for overlay1 and 7.4.10 for cursor as to how to change the overlay/ cursor registers dynamically when the LCD is enabled. Intel® PXA27x Processor Family Specification Update Errata...

  • Page 20: Sleep Mode

    After a few iterations, the tests get into a continuous interrupt loop, where the character timeout interrupt is set, but there is not any data in the FIFO. If the delay loop is placed just outside Intel® PXA27x Processor Family Specification Update...
  • Page 21 Reconfigure the LCD to Dual Panel mode without programming the DMA registers. Enable the LCD Do a quick disable (not normal disable). Program the LCD DMA registers Enable the LCD for operation in Dual Panel mode. Status: No Fix Intel® PXA27x Processor Family Specification Update Errata...
  • Page 22 External USB host connected to the processor USB Client cannot switch correctly between alternate interfaces on the processor USB Client. This issue makes the processor USB Client difficult to be a compound device. Workaround: No Fix Status: Intel® PXA27x Processor Family Specification Update...
  • Page 23 Step 3: a. Enable Overlay 2 in YUV 420 mode. Write to O2CR1. b. Unmask/Clear the input underrun for Channel 2. Wait for input underrun from Channel 2. Write DMA descriptors for Channels 2, 3, and 4. Intel® PXA27x Processor Family Specification Update Errata...
  • Page 24 According to On-the-Go Supplement to the USB 2.0 Specification, we must be able to detect that a Single-Ended Zero (SE0) condition is driven on the USB bus for at least 2 ms before we can initiate a Session Request Protocol (SRP). See paragraph below. Intel® PXA27x Processor Family Specification Update...
  • Page 25 If software requires the entire voltage change sequence to complete, i.e. no more communication with the external power manager IC, the software must wait until the PVCR[VCSA] bit is clear. The following workaround has been tested and will handle all cases. Intel® PXA27x Processor Family Specification Update Errata...
  • Page 26 @ MUST be mapped into pagetable prior to @ this function call @ only stall on the 2nd pass @ compare causes fence on memory transfers @ is this the 2nd pass? @ write to PWRMODE on 2nd pass only Intel® PXA27x Processor Family Specification Update...
  • Page 27 The SD unit always waits a minimum of 1 Ncx cycle between the response and the data block, therefore, the SD unit is not compliant with the 1.01 Spec. Implication: Workaround: Intel® PXA27x Processor Family Specification Update @ update conditional execution counter @ restore interrupts to original state Errata...
  • Page 28 0, r0, c7, c0, 0 @ Set IDLE mrc p14, 0, r0, c7, c0, 0 @ CPWAIT ROUTINE @ read current processor status register @ disable core interrupts @ update the current processor status register Intel® PXA27x Processor Family Specification Update...
  • Page 29 ARM architecture allows the FIQ handler to be placed directly at the FIQ vector (0x0000001c/ 0xffff001c) without requiring a branch. Intel® PXA27x Processor Family Specification Update @ CPWAIT ROUTINE @ CPWAIT ROUTINE...
  • Page 30 MEMC = 208MHz. Note the Turbo bit (T) is not set yet. — Display a code of “0xFFAA0000” — Go to Turbo mode by setting the Turbo bit. — Display a code of “0xFFBB0000” Intel® PXA27x Processor Family Specification Update...
  • Page 31 For example, if you wish to run the core at 156 MHz, then set L=8, N=1.5, T=1, HT=0, A=1, B=1. Intel® PXA27x Processor Family Specification Update // Disable the Core PLL // Enable the Peripheral PLL...
  • Page 32 Slow the speed of the interface down until the card passes. This speed could be as low as 9.75 Workaround: Mbps. Plan Fix Status: // make sure SDCLK1 is running. // turn off free running. // enter self refresh mode. Intel® PXA27x Processor Family Specification Update...
  • Page 33 Note that when switching PSPL, a small glitch might be seen on the Overcurrent indicator for Host Port 3. This should not be an issue since the usage model for PSPL is that it is designed to be set statically at initialization time. Intel® PXA27x Processor Family Specification Update Errata...
  • Page 34 VPO line high, or disconnect by pulling both VPO and VMO low. The USB device must use another method of indicating a connect/disconnect to the Host Port 3, such as using another GPIO, or performing a read to the external device’s status register. When VPMBlockEnbN = 0b1 (original functionality): Intel® PXA27x Processor Family Specification Update...
  • Page 35 According to the specification, CKEN[0] controls the PWM0 and PWM2 Clock Enable, and Problem: CKEN[1] controls the PWM1 and PWM3 Clock Enable. However, CKEN[0] and CKEN[1] both have to be disabled in order to disable any of the PWMx clocks. Intel® PXA27x Processor Family Specification Update Errata...
  • Page 36 Problem: If the 13MHz oscillator is disabled during sleep mode, the processor does not comply to the following statement in section 3.8.1.4 of the Intel® PXA27x Processor Family Developer’s Manual: “When nVDD_FAULT or nBATT_FAULT is asserted, PWER assumes its reset value, enabling only GPIO<1:0>...
  • Page 37 Implication: The block count field in CMD53 is 9 bits (511 maximum blocks). To send more than 511 blocks, set the block count in CMD53 to 0 in the command argument. The PXA27x SDIO controller does not support this functionality.
  • Page 38 1) S/W should not read the CAR[CAIP] bit to determine if a CODEC transaction is in progress Workaround: 2) S/W should not read the CAR[CAIP] bit to determine if a CODEC transaction is in progress Table 6, “Recommended Procedure for Accessing AC97 CODEC Registers” Intel® PXA27x Processor Family Specification Update...
  • Page 39 N o te : A c q u ir in g th e C A R [ C A IP ] lo c k is n o lo n g e r re c o m m e n d e d No Fix Status: Intel® PXA27x Processor Family Specification Update S t e p b y s te p I O C o m p le t io n...

  • Page 40: Specification Changes

    Specification Changes Specification Changes Note: There are no specification changes at this time. Intel® PXA27x Processor Family Specification Update...

  • Page 41: Specification Clarifications

    Specification Clarifications Specification Clarifications Note: There are no specification clarifications at this time. Intel® PXA27x Processor Family Specification Update...
  • Page 42 Documentation Change Documentation Change Note: There are no documentation changes at this time. Intel® PXA27x Processor Family Specification Update...