Hardware, Watchdog, Or Sleep Reset Operation; Memory Controller Pin Reset Values - Intel PXA255 Developer's Manual

Table 6-42. Memory Controller Pin Reset Values
Pin Name
SDCLK [2:0]
SDCKE <1>
SDCKE <0>
DQM [3:0]
nSDCS [3:0]
nWE
nSDRAS
nSDCAS
nOE
MA [25:0]
RDnWR
MD [31:0]
nCS <0>
nCS <5:1>
nPIOIR
nPIOIW
nPOE
nPWE
In sleep mode, the memory pins and controller are in the same state as they are after a hardware
reset, except that the GPIO signals are driven high. If SDRAMs are in self-refresh, they are held
there by setting SDCKE<1> to a 0.
6.11

Hardware, Watchdog, or Sleep Reset Operation

Software performs the following procedures when the processor comes out of a reset:
1. After hardware reset, complete a power-on wait period of 200 µs, which allows the internal
clocks that generate SDCLK to stabilize. Enable MDREFR:K0RUN and E0PIN for
Synchronous Static memory. When MDREFR is written, a refresh interval value
(MDREFR:DRI) must also be written. The following writes are allowed:
a. Write MSC0, MSC1, MSC2
b. Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1
c. Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain
the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must
contain a valid value. Deassert MDREFR:KxFREE.
2. In systems that contain Synchronous Static memory, write to the SXCNFG to configure all
appropriate bits, including the enable bits. Software must perform a sequence that involves a
subsequent write to SXCNFG to change the RAS latencies. While any SMROM banks are
Intel® PXA255 Processor Developer's Manual
PXA255 Processor Reset Value
000
00
1 if BOOT_SEL = Synchronous Memory
0000
1111
1
1
1
1
0x0000000h
0
0x00000000h
1
GPIO Input
GPIO Input
GPIO Input
GPIO Input
GPIO Input
Memory Controller
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