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Intel PXA255 Developer's Manual

Intel PXA255 Developer's Manual

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Intel® PXA255 Processor

Developer's Manual

January, 2004

Order Number:

278693-002

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Page 1 Intel® PXA255 Processor Developer’s Manual January, 2004 Order Number: 278693-002...
Page 2 Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Page 3: Table Of Contents
Power on Reset and Boot Operation ...2-8 2.10 Power Management...2-8 2.11 Pin List ...2-8 2.12 Memory Map...2-18 2.13 System Architecture Register Summary...2-21 Clocks and Power Manager ...3-1 Clock Manager Introduction...3-1 Power Manager Introduction...3-2 Clock Manager...3-2 Intel® PXA255 Processor Developer’s Manual Contents...
Page 4 Clocks and Power Manager Register Summary...3-41 3.9.1 Clocks Manager Register Locations ...3-41 3.9.2 Power Manager Register Summary...3-41 System Integration Unit ...4-1 General-Purpose I/O...4-1 4.1.1 GPIO Operation ...4-1 4.1.2 GPIO Alternate Functions...4-2 4.1.3 GPIO Register Definitions...4-6 Intel® PXA255 Processor Developer’s Manual...
Page 5 DMA Descriptor Address Registers (DDADRx) ...5-20 5.3.5 DMA Source Address Registers ...5-21 5.3.6 DMA Target Address Registers (DTADRx)...5-22 5.3.7 DMA Command Registers (DCMDx) ...5-23 Examples ...5-26 DMA Controller Register Summary ...5-28 Memory Controller ...6-1 Overview...6-1 Functional Description ...6-2 Intel® PXA255 Processor Developer’s Manual Contents...
Page 6 6.10.3 Memory Interface Reset and Initialization...6-78 6.11 Hardware, Watchdog, or Sleep Reset Operation ...6-79 6.12 GPIO Reset Procedure...6-81 6.13 Memory Controller Register Summary ...6-81 LCD Controller...7-1 Overview...7-1 7.1.1 Features...7-2 7.1.2 Pin Descriptions...7-4 LCD Controller Operation ...7-4 Intel® PXA255 Processor Developer’s Manual...
Page 7 SSP Control Register 0 (SSCR0) ...8-8 8.7.2 SSP Control Register 1 (SSCR1) ...8-11 8.7.3 SSP Data Register (SSDR) ...8-15 8.7.4 SSP Status Register (SSSR) ...8-16 SSP Controller Register Summary ...8-19 C Bus Interface Unit ...9-1 Overview...9-1 Signal Description...9-1 Intel® PXA255 Processor Developer’s Manual Contents...
Page 8 10.4.1 Reset ...10-5 10.4.2 Internal Register Descriptions...10-5 10.4.3 FIFO Interrupt Mode Operation ...10-21 10.4.4 FIFO Polled Mode Operation...10-22 10.4.5 DMA Requests...10-22 10.4.6 Slow Infrared Asynchronous Interface...10-23 10.5 UART Register Summary ...10-26 10.5.1 UART Register Differences ...10-28 viii Intel® PXA255 Processor Developer’s Manual...
Page 9 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)...12-17 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)...12-18 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) ...12-20 12.5.10 Case 10: RESET Interrupt ...12-20 12.5.11 Case 11: SUSPEND Interrupt...12-21 12.5.12 Case 12: RESUME Interrupt...12-21 Intel® PXA255 Processor Developer’s Manual Contents...
Page 10 13.6.3 Operational Flow for Accessing CODEC Registers...13-17 13.7 Clocks and Sampling Frequencies ...13-17 13.8 Functional Description ...13-18 13.8.1 FIFOs...13-18 13.8.2 Interrupts...13-19 13.8.3 Registers...13-19 13.9 AC’97 Register Summary ...13-35 Inter-Integrated-Circuit Sound (I2S) Controller...14-1 14.1 Overview...14-1 14.2 Signal Descriptions ...14-2 Intel® PXA255 Processor Developer’s Manual...
Page 11 15.4.4 No Data Command and Response Sequence...15-18 15.4.5 Erase ...15-18 15.4.6 Single Data Block Write ...15-18 15.4.7 Single Block Read ...15-19 15.4.8 Multiple Block Write ...15-20 15.4.9 Multiple Block Read ...15-20 15.4.10 Stream Write ...15-21 15.4.11 Stream Read...15-21 Intel® PXA255 Processor Developer’s Manual Contents...
Page 12 16.5.7 SSP Data Register (SSDR) ...16-28 16.6 Network SSP Serial Port Register Summary...16-29 Hardware UART ...17-1 17.1 Overview...17-1 17.2 Features...17-1 17.3 Signal Descriptions ...17-3 17.4 Operation ...17-3 17.4.1 Reset ...17-4 17.4.2 FIFO Operation...17-4 17.4.3 Autoflow Control ...17-7 Intel® PXA255 Processor Developer’s Manual...
Page 13 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row ...6-32 6-12 SMROM Read Timing Diagram Half-Memory Clock Frequency ...6-39 6-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ...6-41 6-14 Flash Memory Reset Using State Machine ...6-42 Intel® PXA255 Processor Developer’s Manual Contents xiii...
Page 14 LCD Data-Pin Pixel Ordering...7-22 Texas Instruments’ Synchronous Serial Frame* Format...8-4 Motorola SPI* Frame Format...8-5 National Microwire* Frame Format...8-6 Motorola SPI* Frame Formats for SPO and SPH Programming ...8-13 C Bus Configuration Example...9-2 Start and Stop Conditions...9-5 Intel® PXA255 Processor Developer’s Manual...
Page 15 Motorola SPI* Frame Protocol (single transfers) ...16-7 16-5 Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers)...16-8 16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)...16-9 16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ...16-10 Intel® PXA255 Processor Developer’s Manual Contents...
Page 16 PXA255 Processor ID Values...2-4 Effect of Each Type of Reset on Internal Register State ...2-6 Processor Pin Types ...2-8 Pin & Signal Descriptions for the PXA255 Processor...2-9 Pin Description Notes ...2-17 System Architecture Register Address Summary ...2-21 Core PLL Output Frequencies for 3.6864 MHz Crystal ...3-5 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ...3-5...
Page 17 OSMR[x] Bit Definitions ...4-36 4-42 OIER Bit Definitions ...4-36 4-43 OWER Bit Definitions...4-37 4-44 OSCR Bit Definitions ...4-37 4-45 OSSR Bit Definitions...4-38 4-46 PWM_CTRLn Bit Definitions...4-41 4-47 PWM_DUTYn Bit Definitions ...4-42 4-48 PWM_PERVALn Bit Definitions...4-43 Intel® PXA255 Processor Developer’s Manual Contents xvii...
Page 18 6-27 MCATT0/1 Bit Definitions ...6-61 6-28 MCIO0/1 Bit Definitions ...6-61 6-29 Card Interface Command Assertion Code Table...6-62 6-30 MECR Bit Definition...6-63 6-31 Common Memory Space Write Commands ...6-65 6-32 Common Memory Space Read Commands...6-65 xviii Intel® PXA255 Processor Developer’s Manual...
Page 19 9-11 ISR Bit Definitions...9-26 9-12 ISAR Bit Definitions ...9-27 10-1 UART Signal Descriptions ...10-3 10-2 UART Register Addresses as Offsets of a Base ...10-6 10-3 RBR Bit Definitions ...10-6 10-4 THR Bit Definitions ...10-7 Intel® PXA255 Processor Developer’s Manual Contents...
Page 20 12-18 UDCCS4/9/14 Bit Definitions...12-33 12-19 UDCCS5/10/15 Bit Definitions...12-34 12-20 UICR0 Bit Definitions...12-37 12-21 UICR1 Bit Definitions...12-38 12-22 USIR0 Bit Definitions ...12-39 12-23 USIR1 Bit Definitions ...12-41 12-24 UFNHR Bit Definitions ...12-43 12-25 UFNLR Bit Definitions...12-44 Intel® PXA255 Processor Developer’s Manual...
Page 21 14-12 Register Memory Map ...14-16 15-1 Command Token Format...15-2 15-2 MMC Data Token Format ...15-2 15-3 SPI Data Token Format ...15-2 15-4 MMC Signal Description ...15-6 15-5 MMC_STRPCL Bit Definitions ...15-23 15-6 MMC_STAT Bit Definitions ...15-23 Intel® PXA255 Processor Developer’s Manual Contents...
Page 22 15-7 MMC_CLK Bit Definitions ...15-25 15-8 MMC_SPI Bit Definitions ...15-25 15-9 MMC_CMDAT Bit Definitions ...15-26 15-10 MMC_RESTO Bit Definitions...15-27 15-11 MMC_RDTO Register ...15-28 15-12 MMC_BLKLEN Bit Definitions ...15-29 15-13 MMC_NOB Bit Definitions ...15-29 15-14 MMC_PRTBUF Bit Definitions...15-30 15-15 MMC_I_MASK Bit Definitions...15-30 15-16 MMC_I_REG Bit Definitions ...15-32 15-17...
Page 23: Revision History
Revision History Date March 2003 January 2004 Intel® PXA255 Processor Developer’s Manual Revision -001 Initial release Replaced Table 12-13 Modified SSPFRM behavior Added note to Table 3-1 about supported frequencies -002 Explained RDY_sync signal Correct GPIO numbers in Table 4-35...
Page 24 Contents xxiv Intel® PXA255 Processor Developer’s Manual...
Page 25: Introduction
Introduction This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an application specific standard product (ASSP) that provides industry-leading MIPS/mW performance for handheld computing applications. The processor is a highly integrated system on a chip and includes a high-performance low-power Intel XScale® microarchitecture with a variety of different system peripherals.
Page 26: Memory Controller
The USB Client Module is based on the Universal Serial Bus Specification, Revision 1.1. It supports up to sixteen endpoints and it provides an internally generated 48-MHz clock. The USB Device Controller provides FIFOs with DMA access to or from memory. Intel® PXA255 Processor Developer’s Manual...
Page 27: Dma Controller (Dmac)
Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR Communication Port uses the STUART’s transmit and receive pins to directly connect to external IrDA LED transceivers. Intel® PXA255 Processor Developer’s Manual S) Controller S CODECs for digital stereo sound. It...
Page 28: Synchronous Serial Protocol Controller (Sspc)
The modem control pins can be implemented via GPIOs. The STUART has FIFOs with DMA access to or from memory. The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication Port. C) Bus Interface Unit Intel® PXA255 Processor Developer’s Manual...
Page 29: Real-Time Clock (Rtc)
1.2.13.4 Hardware UART (HWUART) The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is programmable up to 921.6 Kbps.
Page 30 Introduction Intel® PXA255 Processor Developer’s Manual...
Page 31: System Architecture
System Architecture Overview The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance, low power portable handheld and handset devices. It incorporates the Intel XScale® microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.
Page 32: Intel Xscale® Microarchitecture Implementation Options
Intel XScale® Microarchitecture Implementation Options The processor incorporates the Intel XScale® microarchitecture which is described in a separate document. This core contains implementation options which an Application Specific Standard Product (ASSP) may elect to implement or omit. This section describes those options.
Page 33: Coprocessor 14 Registers 0-3 - Performance Monitoring
This register may be read by software to determine the device type and revision. The contents of this register for the Intel® PXA255 Processor is defined in the table below. Combined, this register must read as 0x6905 2X0R where R = 0b0000 for the first stepping and then increments for subsequent steppings, and X is the revision of the Intel XScale®...
Page 34: Coprocessor 15 Register 1 - P-Bit
Core Revision [9:4] Product Number [3:0] Product Revision Table 2-3. PXA255 Processor ID Values Stepping 2.2.5 Coprocessor 15 Register 1 - P-Bit Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not implemented in the processor and must be written as zero.
Page 35: I/O Ordering
Generally, all interrupt bits in a unit are ORed together and present a single value to the interrupt controller. Intel® PXA255 Processor Developer’s Manual ; store to external memory address [r2].
Page 36: Reset
(except RTTR) reset reset Intel® PXA255 Processor Developer’s Manual 3-6. shows each pin’s state after each Watchdog Reset Hard Reset reset reset reset reset reset reset reset reset reset...
Page 37: Internal Registers
For this reason some peripherals are mapped to multiple GPIOs, as shown in Alternate Functions” on page peripheral - only that the peripheral is connected to the pins in several ways. Intel® PXA255 Processor Developer’s Manual GPIO Reset Watchdog Reset...
Page 38: Power On Reset And Boot Operation
When nRESET is asserted, nRESET_OUT is driven active and can be used to reset other devices in the system. For additional information, see the Intel® PXA255 Processor Design Guide. When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a specified time later and the device attempts to boot from physical address location 0x0000_0000.
Page 39: Pin & Signal Descriptions For The Pxa255 Processor
Analog bidirectional Supply pin (either VCC or VSS) Table 2-6 describes the PXA255 processor pins. Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9) Pin Name Type Memory Controller Pins Memory address bus. (output) Signals the address MA[25:0] requested for memory accesses.
Page 40 System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9) Pin Name Type SDCLK[1] SDRAM Clocks (output) Connect SDCLK[1] and SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2.
Page 41 Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9) Pin Name Type nPIOW/ PCMCIA I/O write. (output) Performs write transactions ICOCZ to PCMCIA I/O space. GPIO[51] nPIOR/ PCMCIA I/O read. (output) Performs read transactions ICOCZ from PCMCIA I/O space.
Page 42 System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9) Pin Name Type LCD display data. (output) Transfers pixel information L_DD[13]/ from the LCD Controller to the external LCD panel. ICOCZ GPIO[71] 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.
Page 43 Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9) Pin Name Type BTCTS/ ICOCZ Bluetooth UART Clear-to-Send. (input) GPIO[44] BTRTS/ ICOCZ Bluetooth UART Data-Terminal-Ready. (output) GPIO[45] Standard UART and ICP Pins IrDA receive signal. (input) Receive pin for the FIR IRRXD/ function.
Page 44 System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9) Pin Name Type MMCCLK/ MMC clock. (output) Clock signal for the MMC ICOCZ GP[6] Controller. MMCCS0/ MMC chip select 0. (output) Chip select 0 for the MMC...
Page 45 Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9) Pin Name Type AC97 Audio Port data out. (output) Output from the SDATA_OUT/ PXA255 processor to Codecs 0 and 1. ICOCZ GPIO[30] S data out. (output) Output line for the I AC97 Audio Port sync signal.
Page 46 System Architecture Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9) Pin Name Type 48 MHz clock. (output) Peripheral clock output derived from the PLL. 48MHz/GP[7] ICOCZ NOTE: This clock is only generated when the USB unit clock enable is set.
Page 47: Pin Description Notes
If selected as an output, the value contained in the Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.
Page 48: Memory Map
The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each subdivided into I/O, memory and attribute space. Each socket is allocated 256 MB of memory space. 2-18 Description show the full processor memory map. Intel® PXA255 Processor Developer’s Manual...
Page 49: Memory Map (Part One) - From 0X8000_0000 To 0Xffff Ffff
Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF Intel® PXA255 Processor Developer’s Manual 0xFFFF_FFFF Reserved (64 MB) 0xFC00_0000 Reserved (64 MB) 0xF800_0000 Reserved (64 MB) 0xF400_0000 Reserved (64 MB) 0xF000_0000 Reserved (64 MB) 0xEC00_0000 Reserved (64 MB)
Page 50: Memory Map (Part Two) - From 0X0000_0000 To 0X7Fff Ffff
Static Chip Select 4 (64 MB) 0x1000_0000 Static Chip Select 3 (64 MB) 0x0C00_0000 Static Chip Select 2 (64 MB) 0x0800_0000 Static Chip Select 1 (64 MB) 0x0400_0000 Static Chip Select 0 (64 MB) 0x0000_0000 Intel® PXA255 Processor Developer’s Manual...
Page 51: System Architecture Register Summary
0x4000_0130 0x4000_0134 0x4000_0138 0x4000_013C 0x4000_0140 0x4000_0144 0x4000_0148 Intel® PXA255 Processor Developer’s Manual DCSR0 DMA Control / Status Register for Channel 0 DCSR1 DMA Control / Status Register for Channel 1 DCSR2 DMA Control / Status Register for Channel 2 DCSR3...
Page 52 DMA Target Address Register Channel 3 DCMD3 DMA Command Address Register Channel 3 DDADR4 DMA Descriptor Address Register Channel 4 DSADR4 DMA Source Address Register Channel 4 DTADR4 DMA Target Address Register Channel 4 Intel® PXA255 Processor Developer’s Manual Register Description...
Page 53 0x4000_02CC 0x4000_02D0 0x4000_02D4 0x4000_02D8 0x4000_02DC 0x4000_02E0 0x4000_02E4 0x4000_02E8 Intel® PXA255 Processor Developer’s Manual DCMD4 DMA Command Address Register Channel 4 DDADR5 DMA Descriptor Address Register Channel 5 DSADR5 DMA Source Address Register Channel 5 DTADR5 DMA Target Address Register Channel 5...
Page 54 Divisor Latch High Register (DLAB = 1) (read/write) IBMR I2C Bus Monitor Register - IBMR IDBR I2C Data Buffer Register - IDBR I2C Control Register - ICR I2C Status Register - ISR ISAR I2C Slave Address Register - ISAR Intel® PXA255 Processor Developer’s Manual Register Description...
Page 55 0x4050_005C 0x4050_0060 0x4050_0064 through 0x4050_00FC 0x4050_0100 0x4050_0104 0x4050_0108 0x4050_010C 0x4050_0110 Intel® PXA255 Processor Developer’s Manual SACR0 Global Control Register SACR1 Serial Audio I S/MSB-Justified Control Register — Reserved SASR0 Serial Audio I S/MSB-Justified Interface and FIFO Status Register —...
Page 56 UDCCS13 UDC Endpoint 13 (IN) Control/Status Register UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register UFNRH UDC Frame Number Register High UFNRL UDC Frame Number Register Low Intel® PXA255 Processor Developer’s Manual Register Description...
Page 57 0x4070_0008 0x4070_0008 0x4070_000C 0x4070_0010 0x4070_0014 0x4070_0018 0x4070_001C 0x4070_0020 0x4070_0000 0x4070_0004 Intel® PXA255 Processor Developer’s Manual UBCR2 UDC Byte Count Register 2 UBCR4 UDC Byte Count Register 4 UBCR7 UDC Byte Count Register 7 UBCR9 UDC Byte Count Register 9 UBCR12...
Page 58 Interrupt Controller Mask Register ICLR Interrupt Controller Level Register ICFP Interrupt Controller FIQ Pending Register ICPR Interrupt Controller Pending Register ICCR Interrupt Controller Control Register GPLR0 GPIO Pin-Level Register GPIO<31:0> GPLR1 GPIO Pin-Level Register GPIO<63:32> Intel® PXA255 Processor Developer’s Manual Register Description...
Page 59 0x40F0_0008 0x40F0_000C 0x40F0_0010 0x40F0_0014 0x40F0_0018 0x40F0_001C 0x40F0_0020 0x40F0_0024 0x40F0_0028 0x40F0_002C Intel® PXA255 Processor Developer’s Manual GPLR2 GPIO Pin-Level Register GPIO<80:64> GPDR0 GPIO Pin Direction Register GPIO<31:0> GPDR1 GPIO Pin Direction Register GPIO<63:32> GPDR2 GPIO Pin Direction Register GPIO<80:64> GPSR0 GPIO Pin Direction Register GPIO<31:0>...
Page 60 OSCC Oscillator Configuration Register NSSCR0 NSSP Control Register 0 NSSCR1 NSSP Control Register 1 NSSSR NSSP Status Register NSSITR NSSP Interrupt Test Register NSSDR NSSP Data Read/Write Register NSSTO NSSP Time Out Register Intel® PXA255 Processor Developer’s Manual Register Description...
Page 61 0x4400_021C 0x4400_0020 0x4400_0024 0x4400_0038 0x4400_003C 0x4400_0040 0x4400_0044 Memory 0x4800_0000 Controller Intel® PXA255 Processor Developer’s Manual NSSPSP NSSP Programmable Serial Protocol HWRBR Receive Buffer Register (read only) HWTHR Transmit Holding Register (write only) HWIER Interrupt Enable Register (read/write) HWIIR Interrupt ID Register (read only)
Page 62 Card interface I/O Space Socket 1 Timing Configuration MDMRS MRS value to be written to SDRAM Read-only Boot-Time Register. Contains BOOT_SEL and PKG SEL BOOT_DEF values. MDMRSLP Low Power SDRAM Mode Register Set Configuration Register SA1111CR SA1111 Compatibility Register Intel® PXA255 Processor Developer’s Manual Register Description...
Page 63: Clocks And Power Manager
Clocks and Power Manager The Clocks and Power Manager for the PXA255 processor controls the clock frequency to each module and manages transitions between the different power manager (PM) operating modes to optimize both computing performance and power consumption. Clock Manager Introduction The Clocks and Power Manager provides fixed clocks for each peripheral unit.
Page 64: Power Manager Introduction
The processor’s clocking system incorporates five major clock sources: • 32.768 kHz Oscillator • 3.6864 MHz Oscillator • Programmable Frequency Core PLL • 95.85 MHz Fixed Frequency Peripheral PLL • 147.46 MHz Fixed Frequency PLL Intel® PXA255 Processor Developer’s Manual...
Page 65: Clocks Manager Block Diagram
Figure 3-1. Clocks Manager Block Diagram 32.768 k 32.768 3.6864 RETAINS POWER IN SLEEP 47.923 Intel® PXA255 Processor Developer’s Manual Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For 3.6864 3.6864 32.768 k PWR_MGR...
Page 66: 32.768 Khz Oscillator
Section 3.6.3 for more information. No external capacitors are required. Table 3-1, “Core PLL Output Frequencies for Section 3.6.1 for programming information on the L, M, and N factors. Intel® PXA255 Processor Developer’s Manual Section 3.5.2) for the hexadecimal settings.
Page 67: 95.85 Mhz Peripheral Phase Locked Loop
S). The generated frequency may not exactly match the required frequency due to the choice of crystal and the lack of a perfect Least Common Multiple between the units. The chosen frequencies Intel® PXA255 Processor Developer’s Manual Turbo Mode Frequency (MHz) for Values “N”...
Page 68: Clock Gating
To invoke the Hardware Reset and reset all units in the processor to a known state, assert the nRESET pin. Hardware Reset is only intended to be used for power up and complete resets. Nominal Frequency 14.746 MHz 12.288 MHz 146.76 MHz Intel® PXA255 Processor Developer’s Manual Actual Frequency 14.746 MHz 12.288 MHz 147.46 MHz...
Page 69: Watchdog Reset
The nRESET_OUT pin is asserted when the nRESET pin is asserted. To enter Hardware Reset, nRESET must be held low for t state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification for details. 3.4.1.2 Behavior During Hardware Reset During Hardware Reset, all internal registers and units are held at their defined reset conditions.
Page 70: Gpio Reset
Clocks and Power Manager Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” Watchdog and other Resets. 3.4.2.3 Completing a Watchdog Reset Watchdog resets immediately revert to hardware resets when the nRESET pin is asserted. Otherwise, the completion sequence for watchdog reset is: 1.
Page 71: Run Mode
SDRAM refresh interval. The amount of time spent in GPIO Reset depends on the CPU’s mode before GPIO Reset. See Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” PXA255 processor pins during GPIO reset and other resets. 3.4.3.3 Completing GPIO Reset GPIO Reset immediately reverts to Hardware Reset when the nRESET pin is asserted.
Page 72: Idle Mode
CPU clock stops and Idle Mode begins. In Idle Mode, interrupts are recognized as wake-up sources. 3-10 3.6.1). Turbo mode is intended for use during peak processing, when there Intel® PXA255 Processor Developer’s Manual Section 3.7.2). An interrupt...
Page 73: Frequency Change Sequence
3.4.7.1 Preparing for a Frequency Change Sequence Software must complete the following steps before it initiates the Frequency Change Sequence: Intel® PXA255 Processor Developer’s Manual for more details. Clocks and Power Manager Section 3.4.9.3,...
Page 74 Frequency Change Sequence exits. This means that the processor does not enter Sleep Mode until the Frequency Change Sequence is complete. 3-12 Section 6, “Memory Controller” (Section 3.6.1, “Core Clock Configuration Register Intel® PXA255 Processor Developer’s Manual for more details. (CCCR)”) to reflect...
Page 75: 33-Mhz Idle Mode
Note: This sequence occurs even if the before and after frequencies are the same. 2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal Specification for details.
Page 76 Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts that are prevented from interrupting the core based on the Interrupt Controller Mask Register (ICMR). 3-14 Section 3.7.2) Intel® PXA255 Processor Developer’s Manual...
Page 77: Sleep Mode
PWR_EN goes low. • Higher-voltage outputs connected to VCCQ and VCCN are continuously driven and do not change when the PWR_EN pin is asserted. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager 3-15...
Page 78: Entering Sleep Mode
Note: The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast sleep wakeup is selected by setting the PMFW[FWAKE] bit. 3.4.9.3 Entering Sleep Mode Software uses the PWRMODE register to enter sleep mode (See 3-16 Section 6, “Memory Controller” for details. Intel® PXA255 Processor Developer’s Manual Section 3.7.2).
Page 79 Power Manager GPIO Sleep State registers (PGSR0, PGSR1, and PGSR2). To avoid contention on the bus when the processor attempts to wake up, ensure that the chip selects are not set to 0 during sleep mode. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager 3-17...
Page 80: Exiting Sleep Mode
32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to acknowledge the GPIO edge and begin the wake up sequence. Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” on page 2-9 PXA255 processor pin states during sleep mode reset and other resets. 3.4.9.5 Exiting Sleep Mode Sleep Mode exits when Hardware Reset is asserted.
Page 81 5. The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by grounding the VCC and PLL_VCC power supplies to minimize power consumption. Intel® PXA255 Processor Developer’s Manual for details on configuring the SDRAM interface. Clocks and Power Manager...
Page 82: Power Mode Summary
Enable PLL with new frequency Wait for PLL stabilization Wait for internal stabilization Clear CP14 bit 3-20 shows the expected behavior for power supplies in each power mode. Description of Action Description of Action Intel® PXA255 Processor Developer’s Manual Table 3-5 shows the actions...
Page 83 Table 3-5. Power Mode Exit Sequence Table (Sheet 2 of 2) Deassert nRESET_OUT Restart CPU clocks, enable interrupts 1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted. Intel® PXA255 Processor Developer’s Manual Description of Action Clocks and Power Manager 3-21...
Page 84: Power Manager Registers
This section describes the 32-bit registers that control the Power Manager. 3-22 Power Mode Turbo Idle Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck Run/ Turbo (R/T) 3.686 MHz Osc 32.768 kHz Osc Dynamic/ Static (D/S) Intel® PXA255 Processor Developer’s Manual Freq Sleep Change Off Off...
Page 85: Power Manager Control Register (Pmcr)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits Name [31:1] — IDAE Intel® PXA255 Processor Developer’s Manual (PWRMODE)”). The IDAE bit is cleared in any Reset and when Sleep PMCR Description Reserved. Read undefined and must always be written with zeroes. Imprecise Data Abort Enable.
Page 86: Power Manager General Configuration Register (Pcfr)
PGSR register bits. nCS[1], nWE, and nOE are driven high. nOE are affected. appropriate PGSR register bits. Sleep Mode. nPSKTSEL and nPREG are derived from address signals and assume the state of the address bus during Sleep Mode. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager...
Page 87: Power Manager Wake-Up Enable Register (Pwer)
Bits Name WERTC [30:16] — [15:0] Intel® PXA255 Processor Developer’s Manual PWER Description RTC Sleep Mode Wake-up Enable. 0 – Wake-up due to RTC alarm disabled. 1 – Wake-up due to RTC alarm enabled. Cleared on hardware, watchdog, and GPIO resets.
Page 88: Power Manager Rising-Edge Detect Enable Register (Prer)
Sleep mode Rising-edge Wake up Enable 0 – Wake up due to GPx rising-edge detect disabled. 1 – Wake up due to GPx rising-edge detect enabled. Set to 0x 0003 on hardware, watchdog, and GPIO resets. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager...
Page 89: Power Manager Falling-Edge Detect Enable Register (Pfer)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits Name [31:16] — [15:0] Intel® PXA255 Processor Developer’s Manual PFER Description Reserved. Read undefined and must always be written with zeroes. Sleep mode Falling-edge Wake-up Enable 0 – Wake up due to GPx falling-edge detect disabled.
Page 90: Power Manager Gpio Edge Detect Status Register (Pedr)
Sleep mode Edge Detect Status 0 – Wake up on GPx not detected. 1 – Wake up due to edge on GPx detected. Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager...
Page 91: Power Manager Sleep Status Register (Pssr)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits Name [31:6] — — Intel® PXA255 Processor Developer’s Manual Table 3-13, contains the following status flags: Section 3.7.2). PSSR reserved...
Page 92: Power Manager Scratch Pad Register (Pspr)
1 – Chip was placed in sleep mode by setting the sleep mode bit. Cleared by hardware, watchdog, and GPIO resets. Table 3-14, is a holding register that is powered during PSPR Description Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager Clocks and Power Manager...
Page 93: Power Manager Fast Sleep Walk-Up Configuration Register (Pmfw)
PSSR[PH]. If a pin is reconfigured from an input to an output, the register’s last contents are driven onto the pin. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Table 3-15, provides a single bit called FWAKE which is used to select...
Page 94: Pgsr0 Bit Definitions
0 – Pin is driven to a zero during sleep mode 1 – Pin is driven to a one during sleep mode Cleared by hardware, watchdog, and GPIO resets. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager Clocks and Power Manager...
Page 95: Reset Controller Status Register (Rcsr)
The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset state of zero. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual PGSR2 Description...
Page 96: Clocks Manager Registers
1 – Hardware reset has occurred since the last time the CPU cleared this bit. Set by hardware reset. Cleared by setting to a 1. Table 3-20, controls the core clock frequency, from which the core, memory Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager...
Page 97: Cccr Bit Definitions
00100 – reserved 00101 – Multiplier = 45 (Memory Frequency is 165.89MHz from 3.6864 MHz crystal) 00110 to 11111 – reserved Set to 00001 on hardware and watchdog resets. Intel® PXA255 Processor Developer’s Manual Core Clock Configuration Register (CCCR) reserved...
Page 98: Clock Enable Register (Cken)
This bit must be set to allow the 48Mhz clock output on GP7 Alternate Function 1. reserved NSSP Unit Clock Enable 0 – Clock to the unit is disabled 1 – Clock to the unit is enabled. Set by hardware and watchdog resets Intel® PXA255 Processor Developer’s Manual Clocks Manager...
Page 99 CKEN6 CKEN5 CKEN4 CKEN3 CKEN2 CKEN1 CKEN0 Intel® PXA255 Processor Developer’s Manual CKEN Description I2S Unit Clock Enable 0 – Clock to the unit is disabled 1 – Clock to the unit is enabled. Set by hardware and watchdog resets BTUART Unit Clock Enable 0 –...
Page 100: Oscillator Configuration Register (Oscc)
0 – 32.768 KHz oscillator is disabled or not stable. The 3.6864 MHz oscillator (divided by 112) clocks the RTC and PM. 1 – 32.768 KHz oscillator has been enabled (OON=1) and stabilized. It will clock the RTC and PM. Cleared by hardware reset. Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager...
Page 101: Core Clock Configuration Register (Cclkcfg)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits Name [31:2] — TURBO Intel® PXA255 Processor Developer’s Manual Data in Rd — TURBO = 1 FCS = 1 (Turbo mode bit may be set or cleared in the same write)
Page 102: Power Mode Register (Pwrmode)
This can be controlled with an external Power-On-Reset device or another circuit. To ensure that the internal ESD protection devices do not activate during power up, a minimum rise time must be observed. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification for details. 3.8.2 Power Supply Connectivity The processor requires two or three externally-supplied voltage levels.
Page 103: Clocks Manager Register Summary
Some applications have other clock sources of the same frequency and can reduce overall cost by driving the crystal pins externally. Refer to the Oscillator Electrical Specifications in the Intel® PXA255 Processor Design Guide for more information.
Page 104: Power Manager Register Summary
PCFR Power Manager General Configuration register Power Manager GPIO Sleep State register for GP[31-0] Power Manager GPIO Sleep State register for GP[63-32] Power Manager GPIO Sleep State register for GP[84-64] RCSR Reset controller status register Intel® PXA255 Processor Developer’s Manual...
Page 105: System Integration Unit
Pulse Width modulator General-Purpose I/O The PXA255 processor enables and controls its 85 GPIO pins through the use of 27 registers which configure the pin direction (input or output), pin function, pin state (outputs only), pin level detection (inputs only), and selection of alternate functions. A portion of the GPIOs can be used to bring the processor out of Sleep mode.
Page 106: Gpio Alternate Functions
Pin Set and Clear Registers Alternate Functions (Outputs) Edge Detect Edge Status Register Detect Rising Edge Detect Enable Register Falling Edge Detect Enable Register Pin-Level Register Section 3.4.9.5, “Exiting Sleep Mode” on page 3- Intel® PXA255 Processor Developer’s Manual Alternate Functions (Inputs)
Page 107: Gpio Alternate Functions
ALT_FN_2_OUT SYNC ALT_FN_1_OUT GP31 SYNC ALT_FN_2_OUT SDATA_IN1 ALT_FN_1_IN GP32 SYSCLK ALT_FN_1_OUT Intel® PXA255 Processor Developer’s Manual AF{n} Source Unit Signal Description and comments encoding Clocks & Power Active low GP_reset Manager Unit Multimedia Card MMC Clock (MMC) Controller Clocks & Power...
Page 108 HWUART HWUART clear to send Memory Controller I/O Write for Card Space HWUART HWUART request to send Card Enable for Card Space Memory Controller Card Enable for Card Space Multimedia Card MMC Clock (MMC) Controller Intel® PXA255 Processor Developer’s Manual...
Page 109 32 kHz ALT_FN_1_OUT GP72 LDD[14] ALT_FN_2_OUT LDD[15] ALT_FN_2_OUT GP73 MBGNT ALT_FN_1_OUT Intel® PXA255 Processor Developer’s Manual AF{n} Source Unit Signal Description and comments encoding Multimedia Card MMC Clock (MMC) Controller Memory Controller Socket Select for Card Space Card Address bit 26...
Page 110: Gpio Register Definitions
GPLR0 GPLR1 GPSR0 GPSR1 GPCR0 GPCR1 GPDR0 GPDR1 Intel® PXA255 Processor Developer’s Manual Signal Description and comments LCD Frame clock LCD line clock LCD Pixel clock LCD AC Bias Active low chip select 2 Active low chip select 3 Active low chip select 4...
Page 111: Gplr0 Bit Definitions
GPIO Pin Level ‘x’ (where x = 0 to 31). This read-only field indicates the current value of each GPIO. <31:0> PL[x] This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual GPIO[31:16] GPIO[47:32] GRER0 GRER1...
Page 112: Gplr1 Bit Definitions
1 – Pin state is high GPLR2 Description 0 – Pin state is low 1 – Pin state is high Table 4-6, Table 4-7, and Intel® PXA255 Processor Developer’s Manual System Integration Unit System Integration Unit Table 4-8, control whether a pin is...
Page 113: Gpdr0 Bit Definitions
PD[x] 4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output Clear Registers (GPCR0, GPCR1, GPCR2) Intel® PXA255 Processor Developer’s Manual GPDR0 Description 0 – Pin configured as an input 1 – Pin configured as an output...
Page 114: Gpsr0 Bit Definitions
1 – If pin configured as an output, set pin level high (one). GPSR1 Description 0 – Pin level unaffected. 1 – If pin configured as an output, set pin level high (one). Intel® PXA255 Processor Developer’s Manual System Integration Unit System Integration Unit...
Page 115: Gpsr2 Bit Definitions
Bits Name GPIO Pin ‘x’ Output Pin Clear (where x= 32 through 63). <31:0> PC[x] Intel® PXA255 Processor Developer’s Manual GPSR2 Description 0 – Pin level unaffected. 1 – If pin configured as an output, set pin level high (one).
Page 116: Gpcr2 Bit Definitions
Table 4-17 show the bitmaps of the GRER0, GRER1, and GRER2. show the bitmaps of the GFER, GFER1, and GFER2. Intel® PXA255 Processor Developer’s Manual System Integration Unit Table 4-18...
Page 117: Grer0 Bit Definitions
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 64 through 84). <20:0> RE[x] Intel® PXA255 Processor Developer’s Manual GRER0 Description 0 – Disable rising-edge detect enable. 1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin...
Page 118: Gfer0 Bit Definitions
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin GFER2 Description 0 – Disable falling-edge detect enable. 1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin Intel® PXA255 Processor Developer’s Manual System Integration Unit System Integration Unit System Integration Unit...
Page 119: Gedr0 Bit Definitions
Bits Name GPIO Pin ‘x’ Edge Detect Status (where x= 32 through 63). READ <31:0> ED[x] WRITE Intel® PXA255 Processor Developer’s Manual Table 4-21, Table Section 4.2, for a description of the programming of GPIO interrupts. Table 4-23 show the bitmaps of the GEDR0, GEDR1, and GEDR2.
Page 120: Gedr2 Bit Definitions
1 – Edge detect has occurred on pin as specified in GRER and/or GFER. 0 – No effect. 1 – Clear edge detect status field. Table 4-27, Table 4-28, and Table Intel® PXA255 Processor Developer’s Manual System Integration Unit Table 4-24, 4-29, contain select bits that correspond...
Page 121: Gafr0_L Bit Definitions
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1. 10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2. 11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3. Intel® PXA255 Processor Developer’s Manual GAFR0_L Description...
Page 122: Gafr1_L Bit Definitions
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2. 11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3. 4-18 GAFR1_L Description GAFR1_U Description Intel® PXA255 Processor Developer’s Manual System Integration Unit System Integration Unit...
Page 123: Gafr2_L Bit Definitions
GAFR00[31:0] will be 0x0000_ 0000 to indicate normal GPIO function. For simplicity, assume that GP[16-31] are inputs configured as normal GPIOs. In this example, • GPIO[0] is configured as a normal GPIO input Intel® PXA255 Processor Developer’s Manual GAFR2_L Description GAFR2_U reserved...
Page 124: Interrupt Controller
(ICLR) is programmed to send interrupts to the ICIP to generate an IRQ. 4-20 GPIO[12:6], GPIO[13] and GPIO[15] as outputs. This drives – Table 4-29 show the bitmaps of the GPIO Alternate Function registers. – Intel® PXA255 Processor Developer’s Manual identifies all the active interrupts within – contains the interrupts from all...
Page 125: Interrupt Controller Register Definitions
Interrupt Controller Pending register (ICPR) • Interrupt Controller Mask register (ICMR) • Interrupt Controller Level register (ICLR) • Interrupt Controller Control register (ICCR) Intel® PXA255 Processor Developer’s Manual System Integration Unit – contains the interrupts from all All Other Qualified Interrupt Bits Interrupt...
Page 126: Icmr Bit Definitions
Power Manager). 1 – Pending interrupt is allowed to become active (interrupts are sent to CPU and Power Manager). Table 4-31, controls whether a pending interrupt generates an FIQ or Intel® PXA255 Processor Developer’s Manual System Integration Unit reserved...
Page 127: Iclr Bit Definitions
<31:1> — reserved Disable Idle mask. <0> This bit is cleared during all resets. Intel® PXA255 Processor Developer’s Manual ICLR Description 0 – Interrupt routed to IRQ interrupt input. 1 – Interrupt routed to FIQ interrupt input. Table 4-32, contains a single control bit, Disable Idle Mask (DIM). In normal...
Page 128: Icip Bit Definitions
1 – IRQ requested by an enabled source. ICFP Description 0 – FIQ NOT requested by any enabled source. 1 – FIQ requested by an enabled source. Intel® PXA255 Processor Developer’s Manual 4-34, contain one bit per interrupt (22 total.) System Integration Unit reserved System Integration Unit...
Page 129: Icpr Bit Definitions
<24> IS24 MMC Status/Error Detection Interrupt Pending <23> IS23 Intel® PXA255 Processor Developer’s Manual Table 4-35, is a 32-bit read-only register that shows all active interrupts in the ICPR Description 0 – Interrupt NOT pending due to RTC Alarm Match Register.
Page 130 1 – Interrupt pending due to USB service request. 0 – Interrupt NOT pending due to edge detect on one (or more) of GPIO[84:2]. 1 – Interrupt pending due to edge detect on one (or more) of GPIO[84:2]. Intel® PXA255 Processor Developer’s Manual System Integration Unit...
Page 131: List Of First–Level Interrupts
IS<16> Network SSP IS<15> IS<14> AC97 Intel® PXA255 Processor Developer’s Manual ICPR Description 0 – Interrupt NOT pending due to edge detect on GPIO[1]. 1 – Interrupt pending due to edge detect on GPIO[1]. 0 – Interrupt NOT pending due to edge detect on GPIO[0].
Page 132: Real-Time Clock (Rtc)
RCNR. The value of the counter is unaffected by transitions into and out of Sleep or Idle mode. 4-28 Source Unit # of Level 2 Sources Intel® PXA255 Processor Developer’s Manual Bit Field Description I2S interrupt PMU (Performance Monitor) interrupt USB interrupt “OR”...
Page 133: Rtc Register Definitions
31 is used as a Lock Bit. The data in RTTR may be changed only if RTTR[LCK] is cleared. Once, RTTR[LCK] is set to be a one, only a hardware reset can clear the RTTR. Intel® PXA255 Processor Developer’s Manual System Integration Unit Section 4.3.3...
Page 134: Rttr Bit Definitions
The value compared against the RTC counter. 4-30 RTTR Description 0 – RTTR value is allowed to be altered. 1 – RTTR value is not allowed to be altered. RTAR RTMV Description Intel® PXA255 Processor Developer’s Manual System Integration Unit CK_DIV System Integration Unit...
Page 135: Rcnr Bit Definitions
RCNR through the use of the MMU protection mechanisms (refer to the Intel XScale® Microarchitecture for the Intel® PXA255 Processor User’s Manual for details of MMU operation.)
Page 136: Rtsr Bit Definitions
0 – No RTC alarm has been detected. 1 – An RTC alarm has been detected (RTNR matches RCAR).and ALE bit is set Section 4.1, for details on how to make the clock externally visible. To Intel® PXA255 Processor Developer’s Manual System Integration Unit...
Page 137 Accordingly, program the fractional trim to delete 0.92 cycles per second on average to Intel® PXA255 Processor Developer’s Manual -1 32 kHz clocks to be deleted from the input clock stream once per trim...
Page 138: Operating System (Os) Timer
1023 sec 32768 cycles 1 cycle 1 sec -------------------- - ---------------------------------- 32768 1023 sec 5 sec 1 month Error -------------- - ----------------------------- - month 2592000 sec Intel® PXA255 Processor Developer’s Manual 0.002 ppm -1 seconds. 0.03 ppm cycles 1.9 ppm...
Page 139: Watchdog Timer Operation
OS Timer Match register. All four registers are identical, except for location. A single, generic OS Timer match register is described, but all information is common to all four OS Timer Match Registers. Intel® PXA255 Processor Developer’s Manual for details on reset functionality. System Integration Unit Section 3.4.2, “Watchdog...
Page 140: Osmr[X] Bit Definitions
1 – A match between OSMR1 and the OS Timer asserts OSSR[M1]. 0 – A match between OSMR0 and the OS Timer will NOT assert OSSR[M0]. 1 – A match between OSMR0 and the OS Timer asserts OSSR[M0]. Intel® PXA255 Processor Developer’s Manual System Integration Unit System Integration Unit...
Page 141: Ower Bit Definitions
OIER. The OSSR bits are cleared by writing a one to the proper bit position. Writing zeros to this register has no effect. Write all reserved bits as zeros and ignore all reads. Intel® PXA255 Processor Developer’s Manual Table...
Page 142: Pulse Width Modulator
1 – OSMR[1] has matched the OS timer counter. 0 – OSMR[0] has NOT matched the OS timer counter since last being cleared. 1 – OSMR[0] has matched the OS timer counter. Figure Intel® PXA255 Processor Developer’s Manual System Integration Unit 4-3.
Page 143: Pwmn Block Diagram
PWM_CTRLn[PRESCALE]. This divided PWM module clock drives a 10 bit up-counter. This up- counter feeds 2 separate comparators. The first comparator contains the value of PWM_DUTYn[DCYCLE]. When the values match, the PWM_OUT signal is set high. The other Intel® PXA255 Processor Developer’s Manual System Integration Unit 6-bit down counter...
Page 144: Reset Sequence
Note: During abrupt shut down the PWM_OUTn signal may be delayed by up to one PSCLK_PWMn clock period. 4-40 Figure 4-4. 3-36). If the clock is disabled, the unit shuts down in one of two ways: Table 4-46, contains two fields: Intel® PXA255 Processor Developer’s Manual Section 3.6.2, “Clock Enable Section 4.5.2.1.
Page 145: Pwm_Ctrln Bit Definitions
If FDCYCLE=0x0 and DCYCLE=0x0, PWM_OUTn is set low and does not toggle. Note: If FDCYCLE is 0b1, PWM_OUTn is high for the entire period and is not influenced by the value programmed in the DCYCLE bits. Intel® PXA255 Processor Developer’s Manual PWM Control Registers (PWM_CTRL0, PWM_CTRL1)
Page 146: Pwm_Dutyn Bit Definitions
0 – PWM clock (PWM_OUTn) duty cycle is determined by DCYCLE field. 1 – PWM_OUTn is set high and does not toggle. Table 4-48, contains a 10 bit field called PV. This field determines or 64 input clocks per output pulse. Intel® PXA255 Processor Developer’s Manual System Integration Unit DCYCLE...
Page 147: Pulse Width Modulator Output Wave Example
10 (11 clocks) and PWM_DUTYn[DCYCLE] with 6. PWM_CTRLn[PRESCALE] is configured with a value of 0x0 loaded, which results in the PSCLK_PWMn having the same frequency as the 3.6864 MHz input clock. Intel® PXA255 Processor Developer’s Manual PWM Period Control Registers (PWM_PERVAL0, PWM_PERVAL1)
Page 148: System Integration Unit Register Summary
GEDR1 GPIO edge detect status register GPIO[63:32] GEDR2 GPIO edge detect status register GPIO[80:64] GAFR0_L GPIO alternate function select register GPIO[15:0] GPIO alternate function select register GAFR0_U GPIO[31:16] GPIO alternate function select register GAFR1_L GPIO[47:32] Intel® PXA255 Processor Developer’s Manual...
Page 149: Interrupt Controller Register Addresses
OS timer and the physical addresses used to access them. Table 4-52. OS Timer Register Addresses (Sheet 1 of 2) Address 0x40A0_0000 0x40A0_0004 0x40A0_0008 Intel® PXA255 Processor Developer’s Manual GPIO alternate function select register GAFR1_U GPIO[63:48] GPIO alternate function select register GAFR2_L GPIO[79:64]...
Page 150: Pulse Width Modulator Register Addresses
OS timer interrupt enable register Name PWM_CTRL0 PWM0 Control Register PWM_PWDUTY0 PWM0 Duty Cycle Register PWM_PERVAL0 PWM0 Period Control Register PWM_CTRL1 PWM1 Control Register PWM_PWDUTY1 PWM1 Duty Cycle Register PWM_PERVAL1 PWM1 Period Control Register Intel® PXA255 Processor Developer’s Manual Description...
Page 151: Dma Controller
DMA Controller This chapter describes the on-chip DMA controller (DMAC) for the PXA255 processor. The DMAC transfers data to and from main memory in response to requests generated by internal and external peripherals. The peripherals do not directly supply addresses and commands to the memory system.
Page 152: Dmac Channels
Internal peripheral DMA request lines. On chip peripherals send requests using the PREQ signals. On-chip The DMAC does not sample the PREQ signals until it peripherals completely finishes the data transfer from peripheral to the memory. Intel® PXA255 Processor Developer’s Manual Definition...
Page 153: Dma Channel Priority Scheme
If two or more channels are active and request a DMA, the priority scheme in Request priority does not affect requests that have already started. The DMAC priority scheme is considered when the smaller dimension of the DCMDx[SIZE] or DCMDx[LENGTH] is complete. Intel® PXA255 Processor Developer’s Manual dreq_assert_min dreq_assert_min Table 5-6.
Page 154: Channel Priority
S0 > S1 > S2 > S3 S1 > S0 > S3 > S2 S0 > S1 > S2 > S3 S3 > S2 > S1 > S0 Intel® PXA255 Processor Developer’s Manual Number of times served 4 / 8 2 / 8...
Page 155: Dma Descriptors
5. The channel waits for the request or starts the data transfer, as determined by the DCMD[FLOW] source and target bits. 6. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and DCMD[LENGTH]. Intel® PXA255 Processor Developer’s Manual Table 5-4 for priority scheme examples. DMA Channel Priority 0,1,0,1,0,1,0,1,etc.
Page 156: No-Descriptor Fetch Mode Channel State
DCMD[FLOWTRG] = 0 DCMD[FLOWSRC] xor DCMD[FLOWTRG] = 1 Wait request Request Asserted DDADR[STOP] = 1 DDADR[STOP] = 1 Stopped Intel® PXA255 Processor Developer’s Manual Channel Error DDADR[STOP] = 0 Transferring Data DCMD[LENGTH] 0 ≠ & DCMD[FLOWSRC] = 0 & DCMD[FLOWTRG] = 0...
Page 157 DDADR register is loaded and the DCSR[RUN] bit is set to a 1. The DMAC priority scheme does not affect DMA descriptor fetches. The next descriptor is fetched immediately after the previous descriptor is serviced. Intel® PXA255 Processor Developer’s Manual Figure 5-4 summarizes this operation.
Page 158: Channel States
DCMD[FLOWSRC] & DCMD[FLOWTRG] = 0 DCMD[FLOWSRC] xor DCMD[FLOWTRG] = 1 Wait request Request Asserted DDADR[STOP] = 1 DDADR[STOP] = 1 Stopped Intel® PXA255 Processor Developer’s Manual RUN=0 Channel Error DDADR[STOP] = 0 Transferring Data DCMD[LENGTH] 0 ≠ & DCMD[FLOWSRC] = 0...
Page 159: Read And Write Order
DCMD[SIZE] is set to a 1, the memory receives the data in the following order: 1. Byte[0] 2. Byte[1] 3. Byte[2] 4. Byte[3] Intel® PXA255 Processor Developer’s Manual Section 5.3.2 for details. show the progression from state to state. Figure 5-5 for details.
Page 160: Trailing Bytes
The DMA transfers bytes equal to the smaller of DCMD[LENGTH] or DCMD[SIZE]. 5-10 Little Endian DMA Transfers D[0] D[31] DMAC To/From From Word Wide Half-Word Wide Device Device Intel® PXA255 Processor Developer’s Manual from memory From Byte Wide Device...
Page 161: Transferring Data
DTADR, the DCMDx[FLOWTRG] bit must be set to a 1. If DCMDx[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle associated with the byte that caused DCMDx[LENGTH] to decrement to 0. Intel® PXA255 Processor Developer’s Manual DMA Controller Table 5-5...
Page 162 For a flow-through DMA write to an internal peripheral, use the following settings for the DMAC register bits: • DSADR[SRCADDR] = internal peripheral address • DTADR[TRGADDR] = external memory address • DCMD[INCTRGADDR] = 1 • DCMD[FLOWSRC] = 1 • DCMD[FLOWTRG] = 0 5-12 Intel® PXA255 Processor Developer’s Manual...
Page 163: Quick Reference For Dma Programming
AC97 modem transmit audio receive audio transmit receive transmit receive FICP transmit receive STUART transmit receive transmit Intel® PXA255 Processor Developer’s Manual DCMD. Width Width (bytes) (binary) 0x4040_0080 0x4040_0080 0x4020_0000 0x4020_0000 0x4010_0000 0x4010_0000 0x4050_0060 0x4050_0140 0x4050_0140 0x4050_0040 0x4050_0040...
Page 164: Servicing Companion Chips And External Peripherals
DCMD. Width Width (bytes) (binary) 0x4060_0100 0x4060_0180 0x4060_0200 0x4060_0400 0x4060_0600 0x4060_0680 0x4060_0700 0x4060_0900 0x4060_0B00 0x4060_0B80 0x4060_0C00 0x4060_0E00 Intel® PXA255 Processor Developer’s Manual Source Burst Size DRCMR (bytes) Target Target 0x4000_0164 Source 0x4000_0168 Target 0x4000_016C Source 0x4000_0170 Target 0x4000_0178 Source 0x4000_017C...
Page 165 Note: The process shown for a flow-through DMA write to an external peripheral indicates that the external address increases. Some external peripherals, such as FIFOs, do not require an increment in the external address. Intel® PXA255 Processor Developer’s Manual DMA Controller 5-15...
Page 166: Memory-To-Memory Moves
For a memory-to-memory read or write, use these settings for the DMAC registers: • DSADR[SRCADDR] = external memory address • DTADR[TRGADDR] = external memory address • DCMD[INCSRCADDR] = 1 • DCMD[INCTRGADDR] = 1 • DCMD[FLOWSRC] = 0 • DCMD[FLOWTRG] = 0 • DCSR[RUN] =1 5-16 Intel® PXA255 Processor Developer’s Manual...
Page 167: Dmac Registers
Write the read value back to the register to clear the interrupt. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Table 5-6, logs the interrupts for each channel.
Page 168: Dcsrx Bit Definitions
0 – no interrupt if the channel is in uninitialized or stopped state 1 – enables an interrupt if the channel is in uninitialized or stopped state 0 – no pending request 1 – the channel has a pending request Intel® PXA255 Processor Developer’s Manual DMA Controller reserved Section 5.1.4.2...
Page 169 Only one error incidence per channel is logged. The channel that caused the error is updated at the end of the transfer and is accessible after it logs an error until it is reprogrammed and the corresponding run bit is set. Intel® PXA255 Processor Developer’s Manual DMA Channel Control/Status Register (DCSRx)
Page 170: Dma Request To Channel Map Registers (Drcmrx)
1 – Request is mapped to a channel indicated by DRCMRx[3:0] Section 5.1.3 to review the channel priority scheme. Table 5-9) contain the memory address of the next descriptor for a specific Intel® PXA255 Processor Developer’s Manual Table 5-13 DMA Controller CHLNUM...
Page 171: Dma Source Address Registers
32-bit aligned, so bits [1:0] are reserved. DSADR cannot contain the address of any other internal DMA, LCD, or MEMC registers. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual DMA Descriptor Address Register (DDADRx)
Page 172: Dma Target Address Registers (Dtadrx)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 5-22 DMA Source Addr Register (DSADRx) SOURCE ADDRESS Uninitialized Description (Table 5-11) is read only in the Descriptor Fetch Mode and is read/write in Intel® PXA255 Processor Developer’s Manual DMA Controller...
Page 173: Dma Command Registers (Dcmdx)
These registers contain the channel’s control bits and the length of the current transfer in that channel. On power up, the bits in this register are set to 0. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual DMA Target Addr Register (DTADRx)
Page 174: Dcmdx Bit Definitions
0 – no interrupt is generated. 1 – set DCSR[EndIntr] interrupt for the channel when DCMD[LENGTH] is decreased to zero. Indicates that the interrupt is enabled as soon as the data transfer is completed. reserved Intel® PXA255 Processor Developer’s Manual DMA Controller LENGTH...
Page 175 SIZE 15:14 WIDTH — 12:0 LENGTH Intel® PXA255 Processor Developer’s Manual DMA Command Register (DCMDx) Description Device Endian-ness. (read / write). 0 – Byte ordering is little endian 1 – reserved Maximum Burst Size of each data transferred (read / write).
Page 176: Examples
ATM cell), on-the-fly DMA descriptor lists manipulation must be efficient. 1. Write a 0 to DCSR[RUN]. 2. Wait until the channel stops. The channel stop state is reflected in the DCSR:STOPSTATE bit. 5-26 Intel® PXA255 Processor Developer’s Manual...
Page 177 = &desc[1].dsadr desc[0].length = 8; desc[0].dcmd = CMD_IncTrgAdr | CMD_FlowThru; desc[1].ddadr = &desc[0] desc[1].dtadr = I_ADR + I_DATA_OFFS desc[1].dsadr = 0 desc[1].length = 0 desc[1].dcmd = 0 Intel® PXA255 Processor Developer’s Manual DMA Controller Otherwise, continue to Step 5-27...
Page 178: Dma Controller Register Summary
(companion chip request 0) Request to Channel Map Register for DREQ 1 DRCMR1 (companion chip request 1) Request to Channel Map Register for I2S receive DRCMR2 Request Request to Channel Map Register for I2S transmit DRCMR3 Request Intel® PXA255 Processor Developer’s Manual Description...
Page 179 0x4000_0154 0x4000_0158 0x4000_015C 0x4000_0160 0x4000_0164 0x4000_0168 0x4000_016C 0x4000_0170 Intel® PXA255 Processor Developer’s Manual Name Request to Channel Map Register for BTUART receive DRCMR4 Request Request to Channel Map Register for BTUART transmit DRCMR5 Request. Request to Channel Map Register for FFUART receive...
Page 180 DMA Source Address Register channel 4 DTADR4 DMA Target Address Register channel 4 DCMD4 DMA Command Address Register channel 4 DDADR5 DMA Descriptor Address Register channel 5 DSADR5 DMA Source Address Register channel 5 Intel® PXA255 Processor Developer’s Manual Description...
Page 181 0x4000_02C8 0x4000_02CC 0x4000_02D0 0x4000_02D4 0x4000_02D8 0x4000_02DC 0x4000_02E0 0x4000_02E4 0x4000_02E8 Intel® PXA255 Processor Developer’s Manual Name DTADR5 DMA Target Address Register channel 5 DCMD5 DMA Command Address Register channel 5 DDADR6 DMA Descriptor Address Register channel 6 DSADR6 DMA Source Address Register channel 6...
Page 182 DMA Command Address Register channel 14 DDADR15 DMA Descriptor Address Register channel 15 DSADR15 DMA Source Address Register channel 15 DTADR15 DMA Target Address Register channel 15 DCMD15 DMA Command Address Register channel 15 Intel® PXA255 Processor Developer’s Manual Description...
Page 183: Memory Controller
Memory Controller This chapter describes the external memory interface structures and memory-related registers supported by the PXA255 processor. Overview The processor external memory bus interface supports Synchronous Dynamic Memory (SDRAM), synchronous and asynchronous burst modes, Page-mode flash, Synchronous Mask ROM (SMROM), Page Mode ROM, SRAM, SRAM-like Variable Latency I/O (VLIO), 16-bit PC Card expansion memory, and Compact Flash.
Page 184: Functional Description
(nCS[3:0]). Static Bank 4 (16 or 32-bit wide) NOTE: Static Bank 0 must be populated by Static Bank 5 “bootable” memory Intel® PXA255 Processor Developer’s Manual 16-bit PC Card Memory Interface Up to 2-socket support. Requires some external buffering...
Page 185: Static Memory Interface / Variable Latency I/O Interface
Upon enabling an SDRAM partition, a mode register set command (MRS), see sent to the SDRAM devices by writing to the MDMRS register. The PXA255 processor adds support for low-power SDRAM by giving software access to the Extended Mode Register via the MDMRSLP register.
Page 186: 16-Bit Pc Card / Compact Flash Interface
This section provides examples of memory configurations that are possible with the processor. Figure 6-2 shows a system that uses 1M x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Section 6.10.1). Intel® PXA255 Processor Developer’s Manual...
Page 187: Sdram Memory System Example
Figure 6-2. SDRAM Memory System Example nSDCS(2:0) nSDRAS, nSDCAS, nWE, CKE(1) SDCLK(2:1) MA(23:10) 21:10 23:22 15:0 MD(31:0) DQM(3:0) 21:10 23:22 31:16 Intel® PXA255 Processor Developer’s Manual 4Mx16 SDRAM SDRAM nRAS nRAS nCAS nCAS 21:10 addr(11:0) addr(11:0) 23:22 BA(1:0) BA(1:0) DQML...
Page 188: Static Memory System Example
DQ(15:0) DQ(15:0) 2Mx16 SMROM SMROM nRAS nRAS nCAS nCAS 22:10 addr(12:0) addr(12:0) DQML DQML DQMH DQMH 31:16 DQ(15:0) DQ(15:0) Intel® PXA255 Processor Developer’s Manual 2Mx16 SRAM 22:2 addr(20:0) DQML DQMH 15:0 DQ(15:0) 2Mx16 SRAM 22:2 addr(20:0) DQML DQMH 31:16 DQ(15:0)
Page 189: Memory Accesses
Read burst Write single Write burst Write burst Write burst Write burst Intel® PXA255 Processor Developer’s Manual Start Address Description Bits [4:2] Generated by core, DMA, or LCD request. Generated by DMA or LCD request. Generated by cache line fills.
Page 190: Reads And Writes
SDRAM. Both SDRAM partitions in a pair (0/1 or 2/3) must be implemented with the same type of SDRAM devices, but the two partition pairs may differ. Section 6.7.7 Table 6-2, is a read/write register and contains control bits for configuring the Intel® PXA255 Processor Developer’s Manual for more information. Section 6.2.1.
Page 191: Mdcnfg Bit Definitions
10 – 13 row address bits 11 – reserved Number of banks in lower partition pair DNB0 0 – 2 internal SDRAM banks 1 – 4 internal SDRAM banks Intel® PXA255 Processor Developer’s Manual MDCNFG reserved Description Memory Controller Memory Controller...
Page 192 SDRAM data bus width for partition pair 2/3 DWID2 0 – 32 bits 1 – 16 bits 6-10 MDCNFG reserved Description Figure 6-5 for a description of these timing numbers. Intel® PXA255 Processor Developer’s Manual Memory Controller DTC0 Figure 6-4 Section 6.5.4 Table 6-8.
Page 193 Use SA1111 Addressing Muxing Mode for pair 2/3. Setting this bit will override the addressing bit programmed in MDCNFG:DADDR2. DSA1111_2 For an explanation on how the SA1111 addressing works, see 31:29 — reserved Intel® PXA255 Processor Developer’s Manual MDCNFG reserved Description Figure 6-5 for a description of these timing numbers. Memory Controller...
Page 194: Sdram Mode Register Set Configuration Register (Mdmrs)
— reserved 14:7 MDMRS0 MRS value to be written to SDRAM for Partition Pair 0. 6-12 Table 6-3, issues an Mode Register Set (MRS) command to the SDRAM. MDMRS MDCL2 Intel® PXA255 Processor Developer’s Manual Memory Controller MDMRS0 MDCL0 MDBL0...
Page 195 All values in the MDCNFG register must be programmed correctly to ensure proper operation of the SDRAM. The register is used by a low-power SDRAM to control the Partial Array Self- Refresh (PASR) and Temperature Compensated Self-Refresh (TCSR) settings. Intel® PXA255 Processor Developer’s Manual MDMRS MDCL2...
Page 196: Sdram Mdrefr Register (Mdrefr)
1 – Enable low power MRS for Partition Pair 0/1 LOW POWER MRS VALUE TO BE WRITTEN TO SDRAM FOR PARTITION PAIR 0/1 Table 6-5, is a read/write register and contains control bits that refresh both Intel® PXA255 Processor Developer’s Manual Description...
Page 197: Mdrefr Bit Definitions
Section SDRAM Clock Pin 2 (SDCLK2) Divide by 2 Control/Status K2DB2 0 – SDCLK2 is same frequency as MEMCLK 1 – SDCLK2 runs at one-half the MEMCLK frequency Intel® PXA255 Processor Developer’s Manual MDREFR Description 6.7. Memory Controller Memory Controller...
Page 198 0 – SDCLK0 runs at the memory clock frequency. K0DB2 1 – SDCLK0 runs at one-half the memory clock frequency. This bit is automatically set upon hardware or sleep reset. 6-16 MDREFR Description Intel® PXA255 Processor Developer’s Manual Memory Controller...
Page 199: Fixed-Delay Or Return-Clock Data Latching
SDRAM. Program the MDCNFG:DLATCHx and SXCNDF:SXLATCHx fields to a 1 to enable latching using the return clock SDCLK. Intel® PXA255 Processor Developer’s Manual MDREFR Description...
Page 200: Sdram Memory Options
2 x 12 x 9 2 x 12 x 10 2 x 13 x 9 2 x 13 x 10 Table 6-9 for a listing of address mapping options. Intel® PXA255 Processor Developer’s Manual Partition Size (Mbyte/Partition) 16-Bit 32-Bit 2 Mbyte...
Page 201: External To Internal Address Mapping Options
22 21 20 19 18 17 16 15 14 13 12 11 10 1x12x10x32 24 23 22 21 20 19 18 17 16 15 14 13 12 Intel® PXA255 Processor Developer’s Manual Memory Controller External Address pins at SDRAM CAS Time MA<24:10>...
Page 202 22 21 ‘0’ 24 23 ‘0’ 10 9 23 22 ‘0’ 25 24 ‘0’ 11 10 9 24 23 ‘0’ 10 9 26 25 12 ‘0’ 11 10 9 25 24 11 ‘0’ 10 9 Intel® PXA255 Processor Developer’s Manual...
Page 203: External To Internal Address Mapping For Sa-1111 Addressing
22 21 20 19 18 17 16 15 14 13 12 11 10 1x12x10x32 22 21 20 19 18 17 16 15 14 13 12 11 10 Intel® PXA255 Processor Developer’s Manual Memory Controller External Address pins at SDRAM CAS Time MA<24:10>...
Page 204 ‘0’ NOT VALID (illegal addressing combination) 23 22 ‘0’ 24 9 23 22 ‘0’ 23 22 ‘0’ 25 24 9 23 22 ‘0’ 24 9 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination) Intel® PXA255 Processor Developer’s Manual...
Page 205: Pin Mapping To Sdram Devices With Normal Bank Addressing
Use the information below to connect the processor to the SDRAM devices. Some of the addressing combinations may not apply in SA1111 addressing mode. See listing of supported addressing combinations and how to connect the PXA255 processor to the SA1111.
Page 206 1x12x11x32 1x12x11x16 1x13x8x32 1x13x8x16 1x13x9x32 1x13x9x16 1x13x10x32 1x13x10x16 1x13x11x32 1x13x11x16 2x11x8x32 2x11x8x16 2x11x9x32 2x11x9x16 2x11x10x32 2x11x10x16 2x11x11x32 2x11x11x16 2x12x8x32 2x12x8x16 2x12x9x32 2x12x9x16 2x12x10x32 2x12x10x16 6-24 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination) Intel® PXA255 Processor Developer’s Manual...
Page 207: Pin Mapping To Sdram Devices With Sa1111 Addressing
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 1 of 3) # Bits Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA255 processor. Bank x Row x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10...
Page 208 Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 2 of 3) # Bits Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA255 processor. Bank x Row x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10...
Page 209: Sdram Command Overview
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 3 of 3) # Bits Pin mapping to SDRAM devices for SA1111 Addressing Options. MA[24:10] represent the address signals driven from the PXA255 processor. Bank x Row x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10...
Page 210: Sdram Waveforms
Option Value reserved MDMRSx CAS Latency = 2 CAS Latency = 3 Sequential Burst Burst Length = 4 Intel® PXA255 Processor Developer’s Manual MA <24:10> 24:23 22:21 OP code bank bank mask bank bank Figure 6-5 through Figure 6-11.
Page 211: Sdram_Read_Diffbank_Diffrow
CL = 2 clks tRCD tRCD SDCLK nSDCS MA[24:0] nSDRAS nSDCAS DATA DQM[3:0] Intel® PXA255 Processor Developer’s Manual 50ns 100ns tRCD tRCD tRP = 2 clks tRAS = 2 clks tRCD = 2 clks CL = 2 clks 25ns 50ns...
Page 212: Sdram_Read_Samebank_Diffrow
= 5 clks tRCD = 2 clks CL = 2 clks SDCLK nSDCS MA[24:0] bank nSDRAS nSDCAS DATA DQM[3:0] 6-30 50ns tRAS tRAS bank 0000 50ns tRCD tRCD Intel® PXA255 Processor Developer’s Manual 100ns 150ns tRCD tRCD 0000 100ns 0000...
Page 213: Sdram_Write
DTC=00, CL = 2, tRP = 1 clk, tRCD = 1 clk SDCLK[1] SDCKE[1] command read(0) pre(1) nSDCS nSDRAS nSDCAS MA[24:10] MD[31:0] DQM[3:0] RDnWR Intel® PXA255 Processor Developer’s Manual 25ns 50ns tRCD tRCD mask0 mask1 mask2 act(1) bank rd0_0 rd0_1...
Page 214: Synchronous Static Memory Interface
1. SXCNFG[31:16] configures chip select signals 2 and 3. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 6-32 25ns 50ns mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7 Intel® PXA255 Processor Developer’s Manual 75ns 100ns Section 6.7.3) and MSC1, except...
Page 215: Sxcnfg Bit Definitions
101 – 6 clocks 110 – 7 clocks 111 – 8 clocks IF SXTP2 = 10 (non-SDRAM timing Fast Flash), this field is not used and must be programmed to 111. Intel® PXA255 Processor Developer’s Manual SXCNFG SXRL2 SXCL2 Description Section 6.5.4.
Page 216 SX Memory type for partition pair 0/1 00 – Synchronous Mask ROM (SMROM) 13:12 SXTP0 01 – reserved 10 – non-SDRAM-like Synchronous Flash 11 – reserved 6-34 SXCNFG SXRL2 SXCL2 Description Intel® PXA255 Processor Developer’s Manual Memory Controller SXRL0 SXCL0 Section 6.5.4...
Page 217 101 – 6 clocks 110 – 7 clocks 111 – 8 clocks IF SXTP0 = 10 (non-SDRAM timing Fast Flash), this field is not used and must be programmed to 111 Intel® PXA255 Processor Developer’s Manual SXCNFG SXRL2 SXCL2 Description...
Page 218: Sxcnfg
The number of banks per device always defaults to four. 6-36 SXCNFG SXRL2 SXCL2 Description Section 6.10. Intel® PXA255 Processor Developer’s Manual Memory Controller SXRL0 SXCL0...
Page 219: Synchronous Static Memory Mode Register Set Configuration Register (Sxmrs)
MRS command. All values in the SXCNFG register must be programmed correctly to ensure proper device operation (refer to the external memory chip product documentation for proper MRS encoding). Information programmed in the SXCNFG[CL] and Intel® PXA255 Processor Developer’s Manual External Address pins at SXMEM CAS Time 22 21...
Page 220: Synchronous Static Memory Timing Diagrams
MRS value to be written to Synchronous Static Memory requiring an MRS command for 14:0 SXMRS0 Bank Pair 0 6.6.3 Synchronous Static Memory Timing Diagrams Figure 6-12 shows a three-beat read cycle for SMROM. 6-38 SXMRS Description Intel® PXA255 Processor Developer’s Manual Memory Controller SXMRS0...
Page 221: Non-Sdram Timing Sxmem Operation
Flash device. The values for this part number are shown as an example. For Intel part number 28F800F3, programming values for this register to ensure proper operation with the processors are shown in Table 6-17.
Page 222: Frequency Code Configuration Values Based On Clock Speed
Value to Program 8 Word Burst Use rising edge of clock Linear burst Order (INTEL BURST ORDER IS NOT SUPPORTED) nWAIT from the Flash device is ignored by the processor. Hold data for one clock 010 -> CAS Latency 3 011 ->...
Page 223: Burst-Of-Eight Synchronous Flash Timing Diagram (Non-Divide-By-2 Mode)
• nADV asserted time = 1 MEMCLK • MA, nCS setup to nADV asserted = 1 MEMCLK • nADV deasserted to nOE asserted = Code - 2 MEMCLKs Intel® PXA255 Processor Developer’s Manual Valid MDREFR: Frequency K0DB2 Configurations 5 / 6...
Page 224: Asynchronous Static Memory
6.6.4.2 K3 Synchronous StrataFlash Reset The PXA255 processor nRESET_OUT pin must be connected to the K3 #RST pin for Hardware reset, Watchdog reset and sleep mode to work properly. GPIO reset however does not reset the contents of the memory controller configuration register. If GPIO reset operation is required, a...
Page 225 Do not connect MA[1:0] for 32-bit systems. Do not connect MA[0] for 16- bit systems (the PXA255 processor operating in 16-bit mode). For all reads on a 32 bit system DQM[3:0] and MA[1:0] are 0. For all reads on a 16 bit system DQM[1:0] and MA[0] are 0. In the timing diagrams, these byte addresses are shown and referred to as “addr”.
Page 226: Static Memory Sa-1111 Compatibility Configuration Register (Sa1111Cr)
PCI bridge. Normally, when an 8 or 16 bit read is requested, the PXA255 processor asserts all DQM signals and sets the lowest address pins (MA[1:0] for 32 bit external bus and MA[0] for 16 bit external bus) to zero and discards the unwanted portion of data.
Page 227: Bit Byte Address Bits Ma[1:0] For Reads Based On Dqm[3:0]
Reserved SA1111_5 SA1111_4 SA1111_3 SA1111_2 SA1111_1 SA1111_0 Intel® PXA255 Processor Developer’s Manual MA[1:0] MA[0] SA1111 Name Writes must set this field to zero and Read values should be ignored Enables SA-1111 Compatibility Mode for Static Memory Partition 5. Enables SA-1111 Compatibility Mode for Static Memory Partition 4.
Page 228: Asynchronous Static Memory Control Registers (Mscx)
Another exception is non-SDRAM timing Synchronous Flash, which writes asynchronously and requires these programmed values. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 6-46 Table 6-24, are read/write registers and contain control bits for configuring Intel® PXA255 Processor Developer’s Manual...
Page 229: Msc0/1/2 Bit Definitions
RDN1/3/5 Reset Bits Access RBUFFx 14:12 RRRx<2:0> 11:8 RDNx<3:0> Intel® PXA255 Processor Developer’s Manual MSC0 MSC1 MSC2 RDF1/3/5 RT1/3/5 Name Return Data Buffer vs. Streaming behavior. When slower memory devices are being used in the system (e.g. VLIO, slow SRAM/ROM), this bit must be reset to allow the system to not have to remain idle while all data is being read from the device.
Page 230 1 – 16 bits For reset value for RBW0, see This value must be programmed with all memory types including Synchronous Static Memory. This value must not change during normal operation. Intel® PXA255 Processor Developer’s Manual Memory Controller RDN0/2/4 RDF0/2/4 RT0/2/4...
Page 231 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RRR1/3/5 RDN1/3/5 Reset Bits Access RTx<2:0> Intel® PXA255 Processor Developer’s Manual MSC0 MSC1 MSC2 RDF1/3/5 RT1/3/5 Name...
Page 232: Rom Interface
Assert RDF+1 RDF+1 RDF+1 (0,4) RDN+1 (1:3,5:7) RDF+1 RDN+1 (1:7) RDF+1+ RDN+2 waits value, as specified by the ROM manufacturer. Section Intel® PXA255 Processor Developer’s Manual Burst Burst Write Address Assert Assert assert RDF+1 RDN+2 RDN+1 RDF+1 RDF+1 RDF+ RDF+1+...
Page 233: Bit Burst-Of-Eight Rom Or Flash Read Timing Diagram (Msc0[Rdf] = 4 Msc0[Rdn] = 1, Msc0[Rrr] = 1)
MA[25:5] MA[4:2] MA[1:0] nADV(nSDCAS) RDnWR MD[31:0] DQM[3:0] nCS[1] * MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1 Intel® PXA255 Processor Developer’s Manual 6-18, and Figure 6-19 show the timings for burst and non-burst ROMs. 50ns 100ns RDF+2 RDF+2 RDN+1 RDN+1 "00"...
Page 234 = nCS hold from nOE deasserted = 0 ns tDSOH = MD setup to Address changing = 1.5 clk_mems plus board routing delays tDOH = MD hold from Address changing = 0 ns Intel® PXA255 Processor Developer’s Manual 200ns 250ns RRR*2+1...
Page 235: Bit Non-Burst Rom, Sram, Or Flash Read Timing Diagram - Four Data Beats (Msc0[Rdf] = 4, Msc0[Rrr] = 1)
DQM[3:0] are used as byte selects. For all reads, DQM[3:0] are 0b0000. During writes, all 32 data pins are actively driven by the processor regardless of the state of the individual DQM pins. Intel® PXA255 Processor Developer’s Manual RDF+2 RDF+2...
Page 236: Bit Sram Write Timing Diagram (4-Beat Burst (Msc0[Rdn] = 2 Msc0[Rrr] = 1)
= 2 MEMCLKs 6-54 byte addr byte addr byte addr tASW tCES RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 tDSWH mask data bytes mask0 mask1 mask2 Intel® PXA255 Processor Developer’s Manual byte addr tCEH RRR*2+1 RDN+1 RDN+1 mask3...
Page 237: Variable Latency I/O (Vlio) Interface Overview
(nPWE = 1) for this write beat to VLIO. This can result in a period when nCS is asserted, but neither nOE nor nPWE is asserted (this happens when there is a write of 1 beat to VLIO, but all byte enables are turned off). Intel® PXA255 Processor Developer’s Manual 5-24. Memory Controller Table 5-12, “DCMDx Bit...
Page 238: Bit Variable Latency I/O Read Timing (Burst-Of-Four, One Wait Cycle Per Beat) (Msc0[Rdf] = 2, Msc0[Rdn] = 2, Msc0[Rrr] = 1)
= MD setup to Address changing = 1.5 clk_mems plus board routing delays tDOH = MD hold from Address changing = 0 ns tRDYH = RDY Hold from nOE deasserted = 0 ns Intel® PXA255 Processor Developer’s Manual Figure 6-22 shows the timing for 300ns...
Page 239: Bit Variable Latency I/O Write Timing (Burst-Of-Four, Variable Wait Cycles Per Beat)
= nCS held asserted after nOE or nPWE deasserted = 1 MEMCLK • tAH = Address hold after nOE or nPWE deasserted = 1 MEMCLK • nOE or nPWE high time between burst beats = (RDN+2) MEMCLKs Intel® PXA255 Processor Developer’s Manual byte addr byte addr byte addr tASWN...
Page 240: Flash Memory Interface
6.7.7.1 FLASH Memory Timing Diagrams and Parameters Non-burst Flash reads have the same timing as non-burst ROMs reads. timing for writes to non-burst asynchronous Flash. 6-58 Figure 6-23 shows the Intel® PXA255 Processor Developer’s Manual...
Page 241: Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)
= Data, DQM hold after nWE deasserted = 1 MEMCLKs • tCEH = nCS held asserted after nWE deasserted = 1 MEMCLK • tAH = Address hold after nWE deasserted = 1 MEMCLKs Intel® PXA255 Processor Developer’s Manual 50ns 100ns RRR*2+1 RRR*2+1...
Page 242: 16-Bit Pc Card/Compact Flash Interface
MCMEMx registers. Also refer to Figure 6-29 Figure 6-30 for a 16-bit PC Card/Compact Flash timing MCMEM0 MCMEM1 MEMx_HOLD Description Intel® PXA255 Processor Developer’s Manual Memory Controller MEMx_ASST MEMx_SET Table 6-29 for a description of this code and its...
Page 243: Mcatt0/1 Bit Definitions
11:7 affects on the command assertion. Minimum Number of memory clocks to set up address before command assertion for MCIO MCIOx_SET for socket x is equal to MCIOx_SET + 2. Intel® PXA255 Processor Developer’s Manual MCATT0 MCATT1 ATTx_HOLD Description Table 6-29...
Page 244: Card Interface Command Assertion Code Table
(nPIOW) after (nPIOR) after nPWAIT=’1’ nPWAIT=’1’ (2*Code + 3) (2*Code + 4) Intel® PXA255 Processor Developer’s Manual x_ASST_WAIT + x_ASST_HOLD (nPIOW asserted) (nPIOR asserted) # MEMCLKs # MEMCLKs (minimum) (minimum) command command assertion time...
Page 245: Expansion Memory Configuration Register (Mecr)
Must be set by software when at least one card is present and must be cleared when all cards are removed. Number-of-Sockets 0 – 1 Socket 1 – 2 Sockets Intel® PXA255 Processor Developer’s Manual x_ASST_HOLD (nPIOW asserted) (nPIOR asserted) # MEMCLKs...
Page 246: 16-Bit Pc Card Overview
(8 or 16 bits). The PXA255 processor uses nPCE2 to indicate to the expansion device that the upper half of the data bus (MD[15:8]) are used for the transfer, and nPCE1 to indicate that the lower half of the data bus (MD[7:0]) are used.
Page 247: Common Memory Space Write Commands
Table 6-35. 16-Bit I/O Space Write Commands (nIOIS16 = 0) nPCE2 nPCE1 MA<0> nPIOR nPIOW Table 6-36. 16-Bit I/O Space Read Commands (nIOIS16 = 0) nPCE2 nPCE1 MA<0> nPIOR nPIOW Intel® PXA255 Processor Developer’s Manual nPWE MD[15:8] Odd Byte Unimportant...
Page 248: External Logic For 16-Bit Pc Card Implementation
Table 6-38. 8-Bit I/O Space Read Commands (nIOIS16 = 1) nPCE2 nPCE1 MA<0> nPIOR nPIOW 6.8.4 External Logic for 16-Bit PC Card Implementation The PXA255 processor requires external glue logic to complete the 16-bit PC Card socket interface that allows either 1-socket or 2-socket solutions. Figure 6-27 Figure 6-28 pull-ups shown are included as specified in the PC Card Standard - Volume 2 - Electrical Specification.
Page 249: Expansion Card External Logic For A One-Socket Configuration
GPIO pins. In the data bus transceiver control logic, nPCE1 controls the enable for the low byte lane and nPCE2 controls the enable for the high byte lane.\ Intel® PXA255 Processor Developer’s Manual nPCD0...
Page 250: Expansion Card External Logic For A Two-Socket Configuration
PSKTSEL MA(25:0) nPREG nPCE(1:2) nPOE, nPWE nPIOW, nPIOR nPWAIT nPIOIS16 6-68 nPCEx DIR OE# nPOE nPIOR nPCEx Intel® PXA255 Processor Developer’s Manual Socket 0 D(15:0) Socket 1 D(15:0) CD1# CD2# CD1# CD2# RDY/BSY# RDY/BSY# A(25:0) REG# A(25:0) REG# CE(1:2)# IOR#...
Page 251: Expansion Card Interface Timing Diagrams And Parameters
Figure 6-29. 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access MEMCLK MA,nPREG,PSKTSEL nPCE2,nPCE1 nPWE,nPOE,nPIOW,nPIOR RDnWR nIOIS16 nPWAIT read_data write_data Intel® PXA255 Processor Developer’s Manual 50ns x_SET Memory Controller 100ns 150ns x_HOLD x_ASST_HOLD x_ASST_WAIT + wait states 6-69...
Page 252: Companion Chip Interface
Variable Latency I/O (See The connection methods are illustrated in 6-70 100ns IOx_SET IOx_SET IOx_HOLD IOx_ASST_HOLD IOx_ASST_WAIT + wait states Low Byte Section 6.7.6) Figure 6-31 Intel® PXA255 Processor Developer’s Manual 200ns 300ns IOx_HOLD IOx_ASST_HOLD IOx_ASST_WAIT + wait states High Byte Figure 6-32.
Page 253: Alternate Bus Master Mode
Figure 6-31. Alternate Bus Master Mode Processor Figure 6-32. Variable Latency IO Processor Intel® PXA255 Processor Developer’s Manual SDCKE<1> SDCLK<1> nSDCS(0) nSDRAS Memory nSDCAS Controlle MA[25:0] DQM[3:0] MD[31:0] GPIO Block GPIO<13> (MBGNT) GPIO<14> (MBREQ) EXTERNAL SYSTEM nCS(0,1,2,3,4,5) nPWE Memory MA[25:0]...
Page 254: Alternate Bus Master Mode
4. The Alternate master three-states SDRAM outputs prior to time (t + 2 MEMCLKS). 5. The processor drives SDRAM outputs at time (t + 3 MEMCLKS). 6. The processor asserts SDCKE<1> at time (t + 4 MEMCLKS). 6-72 Intel® PXA255 Processor Developer’s Manual...
Page 255 The memory controller prevents the processor from entering sleep until all outstanding transactions have completed. This includes waiting for the MBREQ signal from the alternate master to deassert. For best sleep performance, the alternate master must immediately give up the bus when MBGNT Intel® PXA255 Processor Developer’s Manual Memory Controller 6-73...
Page 256: Options And Settings For Boot Memory
1- 16-bit Synchronous Mask ROM (64 Mbit) 2- 16-bit Synchronous Mask ROMs = 32 bits (64 Mbit each) 1- 16-bit Synchronous Mask ROM (32 Mbit) Table 6-40, contains the boot-up values for the three BOOT_SEL pins and Intel® PXA255 Processor Developer’s Manual Section 6.8. Boot From...
Page 257: Valid Boot Configurations Based On Processor Type
Contains the three inputs pins BOOT_SEL[2:0] for the processor. See BOOT_SEL Time Configurations. Table 6-41. Valid Boot Configurations Based on Processor Type Processor Type (PXA255 processor) Intel® PXA255 Processor Developer’s Manual BOOT_DEF reserved Description Table 6-41 for valid boot configurations. See...
Page 258: Asynchronous Boot Time Configurations And Register Defaults
SXCNFG 0x0004_0004 MDREFR 0x03CA_4FFF E0PIN = 0, K0RUN = 0 MSC0 0x7FF0_7FF8 RBW0 = 1 SXCNFG 0x0004_0004 MDREFR 0x03CA_4FFF E0PIN = 0, K0RUN = 0 BOOT_SEL[2:0] = 000 SXMRS 0000_0000 SXMRS 0000_0000 BOOT_SEL[2:0] = 000 Intel® PXA255 Processor Developer’s Manual...
Page 259: Smrom Boot Time Configurations And Register Defaults
SMROM 16-bit (64 Mbit) (nWORD = ‘0’) MRS value must be 0061h. The number of banks in the device defaults to zero. Intel® PXA255 Processor Developer’s Manual MSC0 7FF0 7FF0 RBW0 = 0 SXCNFG 0004 4531 SXEN0 = 1h, SXCL0 = 4h (CL = 5),...
Page 260: Memory Interface Reset And Initialization
SXEN0 = 1h, SXCL0 = 4h (CL = 5), SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits), SXCA0 = 1h (8-bits), SXTP0 = 0h, SXLATCH=1h MDREFR 03CA 7FFF E0PIN = 1, K0RUN = 1 Intel® PXA255 Processor Developer’s Manual SXMRS 0232 0232 SXMRS 0232 0232 SXMRS...
Page 261: Memory Controller Pin Reset Values
Software must perform a sequence that involves a subsequent write to SXCNFG to change the RAS latencies. While any SMROM banks are Intel® PXA255 Processor Developer’s Manual PXA255 Processor Reset Value 1 if BOOT_SEL = Synchronous Memory...
Page 262 MRS state and back to NOP. The CAS latency must be the only variable option and is derived from the value programmed in the MDCNFG:MDTC0,2 fields. The burst type is programmed to sequential and the length is set to four. 6-80 Intel® PXA255 Processor Developer’s Manual...
Page 263: Gpio Reset Procedure
The SDRAM refresh time is chosen by taking the specified refresh time, typically 64 ms, and sub- tracting the GPIO Reset time (found in the Intel® PXA255 Applications Processors Electrical, Me- chanical, and Thermal Specification). For example, the GPIO Reset time is ~360 microseconds, leaving an SDRAM refresh time of (64 ms - 0.360 ms) = 63.64 ms.
Page 264 Register Name MCIO1 Card interface I/O Space Socket 1 Timing Configuration MDMRS MRS value to be written to SDRAM Read-Only Boot-time register. Contains BOOT_SEL and BOOT_DEF PKG_SEL values. Low-Power SDRAM Mode Register Set Configuration MDMRSLP Register Intel® PXA255 Processor Developer’s Manual...
Page 265: Lcd Controller
LCD Controller The LCD controller provides an interface from the PXA255 processor to a passive (DSTN) or active (TFT) flat panel display. Monochrome and several color pixel formats are supported. Overview The processor LCD controller supports single- or dual-panel displays. Encoded pixel data created by the core is stored in external memory in a frame buffer in 1, 2, 4, 8, or 16-bit increments.
Page 266: Features
Programmable wait-state insertion at the beginning and end of each line • Programmable polarity for output enable, frame clock, and line clock • Programmable interrupts for input and output FIFO underrun • Programmable frame and line clock polarity, pulse width, and wait counts Intel® PXA255 Processor Developer’s Manual...
Page 267: Lcd Controller Block Diagram
Figure 7-1 illustrates a simplified, top-level block diagram for the processor LCD Controller. Figure 7-1. LCD Controller Block Diagram From Clock Module Raw pixel data Intel® PXA255 Processor Developer’s Manual System Bus LCDClk LCD DMA Controller Control Pixel Data Register Data...
Page 268: Pin Descriptions
4. Program FDADRx with the memory address of the palette/frame descriptor, as described in Section 7.6.5.2. 5. Enable the LCD controller by writing to LCCR0, as described in Definition for details. Section Intel® PXA255 Processor Developer’s Manual Section 7.3.5. Section 7.6 7.6.1.
Page 269: Disabling The Controller
DMAC automatically fills the FIFO with a 32-byte burst. Pixel data from the frame buffer remains packed within individual 8-byte entries when it is loaded into the FIFO. If the pixel size is Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 270: Lookup Palette
255 back to 0, as shown in (Table 7-14) and the TMED Control Register (TCR, Time position (frame #) position 1 bit Temporal Modulator Intel® PXA255 Processor Developer’s Manual Table 7-15). Figure 7-2 Pass Filter (Panel) Figure 7-3.
Page 271: Compare Range For Tmed
7. If the matrix output is between these boundaries or the original pixel value is 254 or 255, then the data output to the panel is one. In all other cases, it is zero. Intel® PXA255 Processor Developer’s Manual LB=(PixelValue * Frame#) mod 256 + Offset...
Page 272: Output Fifos
LB =FN x CV + Offset Upper Boundary UB =LB + CV force to 1 Pixel Number Adjustor Chapter 4, “System Integration Unit” Intel® PXA255 Processor Developer’s Manual TCR is the TMED Control Register TSR is the TMED Seed Register Generator Data Generator Generator LB >...
Page 273: Dma
The DMAC automatically performs eight word transfers, filling four entries of the input FIFO. Values are fetched from the bottom of the FIFO, one entry at a time, and each 64-bit value is Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 274: Lcd External Palette And Frame Buffers
0 is at the MSB or the LSB of a word boundary. The ordering of RGB values within the 16-bit entry is fixed for little endian. In palette buffer base programmed in register FSADR. 7-10 Figure 7-5, “Base” is the Intel® PXA255 Processor Developer’s Manual...
Page 275: External Frame Buffer
Figure 7-6. 1 Bit Per Pixel Data Memory Organization 1 bit/pixel Base + Pixel 31 Base + Pixel 63 Intel® PXA255 Processor Developer’s Manual Individual Palette Entry Green (G) unused Little Endian Palette Entry Ordering 4-, 16- or 256-Entry Palette Buffer...
Page 276: Bits Per Pixel Data Memory Organization
Pixel 6 Pixel 5 Pixel 4 Pixel 14 Pixel 13 Pixel 12 Palette Buffer Index<7:0> Pixel 2 Pixel 6 Intel® PXA255 Processor Developer’s Manual Pixel 2 Pixel 1 Pixel 0 Pixel18 Pixel 17 Pixel 16 Pixel 3 Pixel 2 Pixel 1...
Page 277: Bits Per Pixel Data Memory Organization - Passive Mode
56 bytes by adding an extra 5 dummy pixels per line (2.5 bytes) to LCCR1[PPL]. If dummy pixels are to be inserted, the panel must ignore the extra pixel clocks at the end of each line that correspond to the dummy pixels. Intel® PXA255 Processor Developer’s Manual Raw Pixel Data<15:0> Red Data<4:0>...
Page 278: Functional Timing
Bus Bandwidth = 614,400 * 60 = 36.9 MB/sec Functional Timing Figure 7-12 through example used is a 320x240 panel. in active display mode.For precise timing relationships, see the Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification. 7-14 BitsPerPixel Lines ------------------------------------------------------------------------- -...
Page 279: Passive Mode Start-Of-Frame Timing
BLW = Beginning-of-Line Pixel Clock Wait Count - 1 ELW = End-of-Line Pixel Clock Wait Count - 1 PPL = Pixels Per Line - 1 LPP = Lines Per Panel - 1 Intel® PXA255 Processor Developer’s Manual VSP = 0 VSW = 1 VSW = 1...
Page 280: Passive Mode Pixel Clock And Data Pin Timing
PCP - Pixel Clock Polarity 0 - Pixels sampled from data pins on rising edge of clock 1 - Pixels sampled from data pins on falling edge of clock Intel® PXA255 Processor Developer’s Manual Pixels 12 .. 15 Pixels 16 .. 19...
Page 281: Register Descriptions
This field controls the placement of a minimum delay between each LCD DMA request during palette loads to insure enough bus bandwidth is given to other bus masters for accesses. Intel® PXA255 Processor Developer’s Manual PCP = 0 Pixel 1...
Page 282: Lcd Controller Control Register 0 (Lccr0)
DMA request. PDD can be programmed with a 7-18 Section 7.6.5 provides a complete description of how Table 7-3, within all other control registers must be Section 7.6.6 for details. Intel® PXA255 Processor Developer’s Manual...
Page 283 6 bits of green, and 5 bits of blue data; and 5 bits of red, 5 bits of green, and 6 bits of blue data. The RGB format 5:6:5 is normally used, since the human eye can distinguish more shades of green than of red or blue. Intel® PXA255 Processor Developer’s Manual 7-19...
Page 284: Frame Buffer/Palette Output To Lcd Data Pins In Active Mode
LCD’s frame descriptor has been loaded into the internal DMA registers. When SFM=0, the interrupt is enabled, and whenever the start of frame (SOF) status bit in the LCD 7-20 Chapter 4, “System Integration Unit” 4/8/16 Bits/Pixel Mode, Frame Buffer or Palette Entry Intel® PXA255 Processor Developer’s Manual for GPIO...
Page 285: Lcd Controller Data Pin Utilization
Note: In passive color mode, the data pin ordering switches. ordering. Table 7-2. LCD Controller Data Pin Utilization (Sheet 1 of 2) Color/Monochrome Panel Monochrome Monochrome Monochrome Color Intel® PXA255 Processor Developer’s Manual Figure 7-18 Single/ Passive/ Dual Panel Active Panel Single Passive Single...
Page 286: Lcd Data-Pin Pixel Ordering
Blue Green LDD[6] LDD[0] LDD[7] LDD[6] LDD[0] LDD[7] LDD[14] LDD[8] LDD[15] LDD[14] LDD[8] LDD[15] Passive Color Dual-Panel Display Pixel Ordering Intel® PXA255 Processor Developer’s Manual Screen Portion Pins L_DD[7:0] Bottom L_DD[15:8] Whole L_DD[15:0] LDD[1] LDD[2] LDD[3] LDD[0] LDD[1] LDD[2] LDD[3]...
Page 287: Lccr0 Bit Definitions
1 = Quick Disable (QD) status does not generate an interrupt. LCD Disable: 0 = LCD Controller has not been disabled. 1 = LCD Controller has been disabled, or is in the process of disabling. Intel® PXA255 Processor Developer’s Manual Section 7.2.1 LCCR0 Description LCD Controller for more information.
Page 288: Lcd Controller Control Register 1 (Lccr1)
LCD pins. These values must be programmed before enabling the LCD Controller. 7-24 LCCR0 Description interrupt controller). 7-4, contains four bit fields that are used as modulus values for a Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 289 255. 6 extra “dummy” pixel values must be added to the end of each line in the frame buffer. The display being controlled must ignore the dummy pixel clocks at the end of each line. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual 7-25...
Page 290: Lcd Controller Control Register 2 (Lccr2)
L_LCLK does not toggle during the generation of the EFW line clock periods. 7-26 LCD Controller Control Register 1 Description 7-5, contains four bit fields that are used as values for a collection of down Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 291 480 pixels. For portrait mode panels, more than 480 pixels can be used as long as total pixels do not exceed 480,000. For example, a 480x640 portrait mode panel can be used. Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 292: Lcd Controller Control Register 3 (Lccr3)
0b010 = 4-bit pixels 7-28 LCD Controller Control Register 2 Description 7-6, contains bits and bit fields used to control various functions within for details on programming the DMAC to load the palette RAM. BPP Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 293 When ABC is cleared by the CPU, the down counter is enabled and again decrements each time the AC bias pin is inverted. The number of AC bias pin transitions between each interrupt request ranges from 1 to 15. Setting API to 0x0 disables the API function. Intel® PXA255 Processor Developer’s Manual LCD Controller 7-29...
Page 294 The frequency of the pixel clock for a set PCD value or the required PCD value to yield a target pixel clock frequency can be calculated using the two following equations. If double pixel clock mode (DPC) is enabled, PCD must be set greater than or equal to 1. 7-30 Intel® PXA255 Processor Developer’s Manual...
Page 295: Lccr3 Bit Definitions
1 = L_LCLK pin is active low and inactive high. Vertical Sync Polarity: 0 = L_FCLK pin is active high and inactive low. 1 = L_FCLK pin is active low and inactive high. Intel® PXA255 Processor Developer’s Manual LCLK ----------------------------- - 2 PCD –...
Page 296: Lcd Controller Dma
DMA frame descriptors. A frame descriptor is a four-word block, aligned on a 16-byte boundary, in main memory: word[0] contains the value for FDADRx 7-32 LCD Controller Control Register 3 Description Section 7.6.5.2, Section 7.6.5.3, Section Intel® PXA255 Processor Developer’s Manual LCD Controller 7.6.5.4, and Section 7.6.5.5 for more...
Page 297: Fdadrx Bit Definitions
Frame ID Register can be used to hold the initial frame source address. These read-only registers are loaded indirectly via the frame descriptors, as described in Section 7.6.5.1. Intel® PXA255 Processor Developer’s Manual Table 7-7, correspond to DMA channels 0 and 1 and contain the FDADR0...
Page 298: Fsadrx Bit Definitions
Frame ID. — reserved 7-34 FSADR0 FSADR1 Frame Source Address Description 7-9, correspond to DMA channels 0 and 1 and contain an ID field that FIDR0 FIDR1 Frame ID Description Intel® PXA255 Processor Developer’s Manual LCD Controller LCD Controller reserved...
Page 299 These are read-only registers. Ignore reads from reserved bits. Intel® PXA255 Processor Developer’s Manual Table 7-10, correspond to DMA channels 0 and 1 and contain configuration...
Page 300: Ldcmdx Bit Definitions
The two lowest bits [1:0] are part of the length calculation but must always be zero for 20:0 proper memory alignment. LEN = 0 is illegal. 7-36 LDCMD0 LDCMD1 Description frame (after loading the frame descriptor). last word of this frame. fetching the last word of this frame. Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 301: Lcd Dma Frame Branch Registers (Fbrx)
0 = Do not branch after finishing the current frame. 1 = Branch after finishing the current frame. The next descriptor will be fetched from the Intel® PXA255 Processor Developer’s Manual Table 7-11, contain the addresses, aligned on a 4-byte...
Page 302: Lcd Controller Status Register (Lcsr)
FIFOs are filled and emptied at the same time, so that underrun occurs at the same time for both 7-38 7-12, contains bits that signal: Section 4.2, “Interrupt Controller” on page 4-20 Intel® PXA255 Processor Developer’s Manual for more details.
Page 303 (LCCR0[LDM] = 0). LDD remains set until cleared by software. Performing a quick disable by clearing LCCR0[ENB] does not set LDD. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual 7-39...
Page 304: Lcsr Bit Definitions
FIFO. pin has toggled the number of times specified by the LCCR3[API] control-bit field. The counter is reloaded with the value in API but is disabled until the user clears ABC. Intel® PXA255 Processor Developer’s Manual LCD Controller...
Page 305: Lcd Controller Interrupt Id Register (Liidr)
Bits Name 31:3 IFRAMEID Interrupt Frame ID — reserved Intel® PXA255 Processor Developer’s Manual LCD Controller Status Register 1 reserved Description 7-13, contains a copy of the Frame ID Register (FIDR) from the descriptor LCD Controller Interrupt ID Register IFRAMEID...
Page 306: Tmed Rgb Seed Register (Trgbr)
TME Blue Seed value 15:8 TME Green Seed value TME Red Seed Value 7-42 Table 7-14 contains the three (red, green, blue) eight-bit seed values used by the TMED RGB Seed Register 0xAA Description Intel® PXA255 Processor Developer’s Manual LCD Controller 0x55 0x00...
Page 307: Tmed Control Register (Tcr)
A 1 will select the (recommended) TMED2 matrix, and a 0 will select the older TMED matrix. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual 7-15, selects various options available in the TMED dither algorithm. There LCD Controller Section 7.3.3.
Page 308: Lcd Controller Register Summary
LCD controller control register 0 LCCR1 LCD controller control register 1 LCCR2 LCD controller control register 2 LCCR3 LCD controller control register 3 FBR0 DMA channel 0 frame branch register Intel® PXA255 Processor Developer’s Manual LCD Controller THBS TVBS Description...
Page 309 0x4400_0040 0x4400_0044 0x4400_0200 0x4400_0204 0x4400_0208 0x4400_020C 0x4400_0210 0x4400_0214 0x4400_0218 0x4400_021C Intel® PXA255 Processor Developer’s Manual Name FBR1 DMA channel 1 frame branch register LCSR LCD controller status register LIIDR LCD controller interrupt ID register TRGBR TMED RGB Seed Register TMED Control Register...
Page 310 LCD Controller 7-46 Intel® PXA255 Processor Developer’s Manual...
Page 311: External Interface To Codec
Synchronous Serial Port Controller This chapter describes the Synchronous Serial Port Controller’s (SSPC) signal definitions and operation for the PXA255 processor usage. Overview The SSPC is a full-duplex synchronous serial interface and can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial protocols for transferring data.
Page 312: Functional Description
SSPSFRM–Depending on the transmission format selected, defines the boundaries of a data frame, or marks the beginning of a data frame. • SSPTXD–Transmit signal for outbound data, from system to peripheral. Chapter 4, “System Chapter 5, “DMA Intel® PXA255 Processor Developer’s Manual...
Page 313 SSPSCLK. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSPSCLK after the last bit has been latched. Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller...
Page 314: Texas Instruments' Synchronous Serial Frame* Format
Bit<N- Bit<N> Bit<1> Bit<0> 1> Bit<N- Bit<N> Bit<1> Bit<0> 1> 4 to 16 Bits Single Transfer Bit<N- Bit<1> Bit<0> Bit<N> 1> Continuous Transfers Intel® PXA255 Processor Developer’s Manual Bit<N- Bit<1> Bit<0> 1> Section 8.7.2...
Page 315: Motorola Spi* Frame Format
The start and end of a series of back-to-back transfers are similar to those of a single transfer. However, SSPSFRM remains asserted (low) throughout the transfer. The end of a data word on SSPRXD is immediately followed by the start of the next command byte on SSPTXD. Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller Bit<N- Bit<N>...
Page 316: Parallel Data Formats For Fifo Storage
Logic in the SSPC automatically left-justifies data in the Transmit FIFO so the sample is properly transmitted on SSPTXD in the selected frame format. Bit<0> 1 Clk Bit<N> 4 to 16 Bits Single Transfer Bit<7> Bit<N> Bit<0> Continuous Transfers Intel® PXA255 Processor Developer’s Manual Bit<0> Bit<0> 1 Clk Bit<N> Bit<0>...
Page 317: Fifo Operation And Data Transfers
7.2 kbps to 1.8432 Mbps. Setting the External Clock Select (ECS) bit to 1 enables an external clock (SSPEXTCLK) to replace the 3.6864 MHz standard internal clock. The external clock is also divided by 2 before it is fed to the programmable divider. Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller Section 8.7.4) to determine how many samples...
Page 318: Ssp Serial Port Registers
SSP is disabled. The reset states for the other control bits are shown in the table, but each reset state must be set to the desired value before the SSPC is enabled. 8-2, contains five bit fields that control SSP data size, frame format, Intel® PXA255 Processor Developer’s Manual...
Page 319: Sscr0 Bit Definitions
16 bits, received data is automatically right-justified and the upper bits in the receive FIFO are zero-filled by receive logic. Do not left-justify transmit data before placing it in the Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller...
Page 320 GPIO sleep register. SSPC register settings have no effect on the pins in Sleep mode. 8-10 Chapter 4, “System Integration Unit” Chapter 4, “System Integration Unit”. In Sleep Intel® PXA255 Processor Developer’s Manual...
Page 321: Sscr1 Bit Definitions
Microwire Transmit Data Size: MWDS 0 = 8-bit command words are transmitted. 1 = 16-bit command words are transmitted. Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller 8-3, contains bit fields that control SSP functions. SSP Control Register 1 (SSCR1) Description frame.
Page 322 1. Sets threshold level at which Receive FIFO generates an interrupt or DMA request. This level must be set to the desired threshold value minus 1. reserved Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller...
Page 323: Motorola Spi* Frame Formats For Spo And Sph Programming
SSPSCLK and SSPSFRM, shifting the SSPSCLK signal one-half phase to the left or right during the SSPSFRM assertion. Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming SSPSCLK SPO=0 SSPSCLK SPO=1 SSPSFRM SSPTXD Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller Bit<N> > Bit<1> Bit<0> Bit<N-1 8-13...
Page 324 4 to 16 Bits SPH = 0 Bit<N- Bit<N> Bit<1> Bit<0> 1> Bit<N- Bit<N> Bit<1> Bit<0> 1> 4 to 16 Bits SPH = 1 Table 8-4 Table 8-4 Intel® PXA255 Processor Developer’s Manual for suggested TFT values for suggested RFT values...
Page 325: Ssdr Bit Definitions
Data word to be written to/read from Transmit/Receive FIFO (Low Word) 31:16 — reserved Intel® PXA255 Processor Developer’s Manual TFT Value RFT Value Min Max Min 8-5, is a single address location that can be accessed by read/write data SSP Data Register (SSDR)
Page 326: Ssp Status Register (Sssr)
All bits are read-only except ROR, which is read/write. ROR’s reset state is zero. Writes to TNF, RNE, BSY, TFS, and RFS have no effect. Writes to reserved bits are ignored and reads from these bits are undetermined. 8-16 Table 8-6. The SSSR contains bits that signal overrun Intel® PXA255 Processor Developer’s Manual...
Page 327: Sssr Bit Definitions
FIFO is completely full. This bit can be polled when using programmed I/O to fill the transmit FIFO over its threshold level. This bit does not request an interrupt. Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller SSP Status Register (SSSR)
Page 328 The ROR bit’s setting does not generate any DMA service request. Writing 0b1 to this bit resets ROR status and its interrupt request. Writing a “0” does not affect ROR status. 8.7.4.7 Transmit FIFO Level (TFL) This bit indicates the number of entries currently in the Transmit FIFO. 8-18 Intel® PXA255 Processor Developer’s Manual...
Page 329: Ssp Controller Register Summary
SSP registers associated with the SSP controller and their physical addresses. Table 8-7. SSP Controller Register Summary Address 0x4100_0000 0x4100_0004 0x4100_0008 0x4100_000C 0x4100_0010 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller Abbreviation SSCR0 SSP Control Register 0 SSCR1 SSP Control Register 1 SSSR SSP Status Register —...
Page 330 Synchronous Serial Port Controller 8-20 Intel® PXA255 Processor Developer’s Manual...
Page 331: C Bus Interface Unit
C Bus Interface Unit This chapter describes the Inter-Integrated Circuit (I2C) bus interface unit, including the operation modes and setup for the PXA255 processor. Overview The I C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface.
Page 332 Processor Gate Array C interfaces to the I C bus. Two masters can drive the bus simultaneously, Intel® PXA255 Processor Developer’s Manual C reads data, it is a master- EEPROM Micro - Controller C bus arbitration relies on the wired-AND...
Page 333: Operational Blocks
C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the bus and receive any slave addresses intended for the processor. Intel® PXA255 Processor Developer’s Manual C bus. Polling can be used instead of interrupts. The C bus, an 8-bit buffer for passing data to and Section 9.9.4...
Page 334: Start And Stop Bus States
In master-receive mode, the ICR[ACKNAK] must be changed to a negative ACK (see bit, receives the data byte in the IDBR, and sends a STOP condition on the I Intel® PXA255 Processor Developer’s Manual C Slave Section 9.4.8), the interface either C unit remains in Section 9.4.6...
Page 335: Start And Stop Conditions
9-2). In master-receive mode, the I ICR[STOP] bit, and the ICR[TB] bit to initiate the last transfer. Software must clear the ICR[STOP] condition after it is transmitted. Intel® PXA255 Processor Developer’s Manual Start Condition Section 9.9.2). The START and the IDBR contents are transmitted on the C bus stays in master-transmit mode for write requests C unit.
Page 336: Start And Stop Conditions
C Bus Interface Unit Figure 9-3. START and STOP Conditions No START or STOP Condition ACK/ Data byte START Condition START Target Slave Address R/nW STOP Condition ACK/ Data Byte STOP Intel® PXA255 Processor Developer’s Manual ACK/...
Page 337: I2C Bus Operation
4. After the CPU reads the IDBR, the I bit, allowing the next byte transfer to proceed. Intel® PXA255 Processor Developer’s Manual C Slave Address Register (ISAR) manage data and Section 9.9.2) contains one byte of data or a 7-bit slave address...
Page 338: I2C Acknowledge
C unit reads the first seven bits and C unit reads the eighth bit (R/nW bit) and transmits an ACK pulse. The for actions when a general call address is detected. Figure 9-5). Intel® PXA255 Processor Developer’s Manual C unit transitions to master- C bus...
Page 339: Polling
The I C bus’ multi-master capabilities require I two or more masters generate a START condition in the minimum hold time. Intel® PXA255 Processor Developer’s Manual C Bus C unit sends a negative acknowledge (NAK) to signal the slave- C bus protocol, the ISR[BED] bit is not set for a master-...
Page 340: Clock Synchronization During The Arbitration Procedure
9-6). A clock cannot switch from low to high if another master has The master with the longest clock period holds the SCL line low. Figure 9-7 shows the arbitration procedure for two Intel® PXA255 Processor Developer’s Manual C interfaces to the SCL line. Start Counting High Period Wait...
Page 341: Arbitration Procedure Of Two Masters
When arbitration is resolved, the winning master sends a restart and begins a valid data transfer. The slave discards the master’s address and use the other data. Intel® PXA255 Processor Developer’s Manual Transmitter 1 Leaves Arbitration Data 1 SDA C bus becomes free.
Page 342: Master Operations
C unit attempts to resend it when the bus becomes free. • System designer must ensure boundary conditions described in Section 9.4 do not occur. Intel® PXA255 Processor Developer’s Manual C unit transitions from the default C unit enters one of two master modes: describes the I C unit’s...
Page 343 C unit transitions to master-receive mode and waits to receive the read data from the slave device (see Figure example, transitioning from master-receive to master-transmit through a repeated start. Intel® PXA255 Processor Developer’s Manual Mode of Operation • I C master operation data transmit mode.
Page 344: Master-Receiver Read From Slave-Transmitter / Repeated Start / Master Transmitter Write To Slave-Receiver
Byte Byte N Bytes + ACK Repeated Start Data Chaining Slave to Master Data R/nW C unit operates as a slave device. Intel® PXA255 Processor Developer’s Manual Data STOP Byte N Bytes + ACK R/nW Data Data STOP Byte Byte...
Page 345: Slave Transactions
Slave-transmit from master- only receiver Figure 9-11 through between master and slave devices. Intel® PXA255 Processor Developer’s Manual Mode of Operation • I C unit monitors all slave address transactions. • ICR[IUE] bit must be set. • I C unit monitors bus for START conditions. When a START is...
Page 346: Master-Receiver Read To Slave-Transmitter, Repeated Start, Master Transmitter Write To Slave-Receiver
N Bytes + ACK Repeated START Data Chaining Slave to Master Figure 9-14 shows a general call address transaction. The least significant bit of Table 9-7 Intel® PXA255 Processor Developer’s Manual Data STOP Byte N Bytes + ACK Data STOP Byte...
Page 347: General Call Address Second Byte Definitions
When B=1, the sequence is a hardware general call and is not supported by the I the The I C-Bus Specification for information on hardware general calls. C 10-bit addresses and CBUS compatibility are not supported. Intel® PXA255 Processor Developer’s Manual C unit, it must set the ICR[GCD] bit to prevent Second Byte Second Byte...
Page 348: Slave Mode Programming Examples
Read ISR: Slave Address Detected (1), Unit busy (1), R/nW bit (0) 2. Write a 1 to the ISR[SAD] bit to clear the interrupt. 3. Return from interrupt. 4. Set ICR[TB] bit to initiate the transfer. 9-18 C unit. Intel® PXA255 Processor Developer’s Manual C unit...
Page 349: Master Programming Examples
Read ISR: IDBR Transmit Empty (1), Unit busy (x), R/nW bit (0) 9. Write a 1 to the ISR[ITE] bit to clear the interrupt. 10. Clear ICR[STOP] bit. Intel® PXA255 Processor Developer’s Manual C unit will keep SCL low until C bus and allow next transfer.
Page 350: Read 1 Byte As A Master
Clear ICR[START], set ICR[STOP], set ICR[ALDIE], set ICR[ACKNAK], set ICR[TB] 15. When an IDBR Receive full interrupt occurs (unit is sending stop). Read ISR: IDBR Receive Full (1), Unit Busy (x), R/nW bit (1), ACK/NAK bit (1) 9-20 Intel® PXA255 Processor Developer’s Manual...
Page 351: Read 2 Bytes As A Master - Send Stop Using The Abort
C bus is idle when the unit is enabled after reset. When directed to reset, the I unit, except for ISAR, returns to the default reset condition. ISAR is not affected by a reset. Intel® PXA255 Processor Developer’s Manual C unit is not busy before it asserts a reset. Software must also...
Page 352: Register Definitions
C unit to the IDBR and sends it to the serial bus. C bus and the acknowledge cycle is complete. If the C unit inserts wait states until the processor writes the Intel® PXA255 Processor Developer’s Manual C MMRs remain intact. When C bus is hung and C Bus Interface Unit C bus.
Page 353: I2C Control Register (Icr)
1 = Enables the I Slave STOP Detected Interrupt Enable: 0 = Disable interrupt. SSDIE 1 = Enables the I Intel® PXA255 Processor Developer’s Manual C Data Buffer Register reserved C Data Buffer: Buffer for I C bus send/receive data.
Page 354 C clock output for master mode operation. C unit transmits STOP using the STOP ICR bit only. C unit sends STOP without data transmission. C unit when the byte is sent/received. Intel® PXA255 Processor Developer’s Manual C Bus Interface Unit C bus errors: 9.7.
Page 355: I2C Status Register (Isr)
• Arbitration Lost This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual C Control Register C unit sends an ACK pulse after it receives a data byte. C unit sends a negative ACK (NAK) after it receives a data byte.
Page 356: Isr Bit Definitions
C unit is using the bus (i.e., unit busy). C bus is busy but the I C unit not busy. C unit is busy. Defined as the time between the first START and STOP. Intel® PXA255 Processor Developer’s Manual C Bus Interface Unit Section 9.4.5.
Page 357: Isar Bit Definitions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset 31:7 — reserved mode. Intel® PXA255 Processor Developer’s Manual C Status Register reserved C unit received or sent an ACK on the bus. C unit received or sent a NAK. C unit is in master-transmit or slave-receive mode.
Page 358 C Bus Interface Unit 9-28 Intel® PXA255 Processor Developer’s Manual...
Page 359: Uarts
UARTs This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports. The serial ports are controlled via direct memory access (DMA) or programmed I/O. The PXA255 processor has four UARTs: Full Function UART (FFUART), Bluetooth UART (BTUART), Standard UART (STUART) and Hardware UART (HWUART). The HWUART is covered in Chapter 17.
Page 360: Overview
16550’s functions as well as the following features: • DMA requests for transmit and receive data services • Slow infrared asynchronous interface • Non-Return-to-Zero (NRZ) encoding/decoding function 10-2 Section Section 10.1), but does not support Intel® PXA255 Processor Developer’s Manual 10.1) but...
Page 361: Uart Signal Descriptions
Table 10-1. UART Signal Descriptions (Sheet 1 of 2) Name nCTS nDSR nDCD Intel® PXA255 Processor Developer’s Manual for details on the GPIOs. Type SERIAL INPUT: Serial data input to the receive shift register. In infrared Input mode, it is connected to the infrared receiver input. This signal is present on all three UARTs.
Page 362: Uart Operational Description
This signal is used by the FFUART and BTUART. Figure 10-1. Data Data Data Data Data <1> <2> <3> <4> <5> Intel® PXA255 Processor Developer’s Manual Description Parit Data Data Stop Stop <6> <7> Bit 1 Bit 2...
Page 363: Reset
UART is 32 bits. The state of the SLCR[DLAB] bit affects the selection of some UART registers. To access the Baud Rate Generator Divisor Latch registers, software must set the SLCR[DLAB] bit high. Intel® PXA255 Processor Developer’s Manual 4-1) then set IER[UUE]. When the UART is UARTs...
Page 364: Receive Buffer Register (Rbr)
Modem Status (read only) Scratch Pad (read/write) Infrared Selection (read/write) Divisor Latch Low (read/write) Divisor Latch High (read/write) Table 10-3, holds the character received by the UART’s Receive Buffer Register reserved Description Intel® PXA255 Processor Developer’s Manual Register Accessed UART...
Page 365: Thr Bit Definitions
The divisor’s reset value is 0x0002. For the FFUART and the STUART, the divisor must be set to at least 0x0004 before the UART unit is enabled. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Table 10-4, holds the data byte that is to be transmitted...
Page 366: Dlh Bit Definitions
DMA requests are disabled because an error interrupt only occurs when DMA requests are enabled. 10-8 Divisor Latch Low Register reserved Description Divisor Latch High Register reserved Description Table 10-7, enables the five types of interrupts that set a value in the Interrupt Intel® PXA255 Processor Developer’s Manual UART UART...
Page 367: Ier Bit Definitions
Interrupt Identification Register (IIR) The UART prioritizes interrupts in four levels (see IIR, shown in Table and identifies the source of the interrupt. Intel® PXA255 Processor Developer’s Manual Interrupt Enable Register reserved Description Table 10-9, stores information that indicates that a prioritized interrupt is pending...
Page 368: Interrupt Conditions
Transmitter requests data. In FIFO mode, the transmit FIFO is at least half empty. In non-FIFO mode, the THR has been transmitted. Modem Status: one or more modem input signal has changed state. Interrupt Identification Register reserved Description Intel® PXA255 Processor Developer’s Manual UART...
Page 369: Interrupt Identification Register Decode
Interrupt Pending: 0 – Interrupt is pending (Active low) 1 – No interrupt is pending Table 10-10. Interrupt Identification Register Decode (Sheet 1 of 2) Interrupt ID Bits Intel® PXA255 Processor Developer’s Manual Interrupt Identification Register reserved Description Interrupt SET/RESET Function...
Page 370: Fcr Bit Definitions
10-11, is a write-only register that is located at the same address as the FIFO Control Register reserved Description Intel® PXA255 Processor Developer’s Manual Reading the Receiver FIFO, setting FCR[RESETRF] or a new start bit is received Non-FIFO mode: Reading...
Page 371 The LCR has bits that allow access to the Divisor Latch and bits that can cause a break condition. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual FIFO Control Register reserved...
Page 372: Lcr Bit Definitions
Word Length Select: Specifies the number of data bits in each transmitted or received character. 00 – 5-bit character WLS[1:0] 01 – 6-bit character 10 – 7-bit character 11 – 8-bit character 10-14 Line Control Register reserved Description Intel® PXA255 Processor Developer’s Manual UART...
Page 373: Lsr Bit Definitions
0 – There is data in the Transmit Shift Register, the Transmit Holding Register, or the FIFO 1 – All the data in the transmitter has been shifted out Intel® PXA255 Processor Developer’s Manual Table 10-13, provides data transfer status information to the processor.
Page 374 FIFO, not for the most recently received character. 0 – No Framing error 1 – Invalid stop bit has been detected 10-16 Line Status Register reserved Description Intel® PXA255 Processor Developer’s Manual UART...
Page 375 In FIFO mode, DR is cleared if the FIFO is empty (last character has been read from RBR) or the FIFO is reset with FCR[RESETRF]. 0 – No data has been received 1 – Data is available in RBR or the FIFO Intel® PXA255 Processor Developer’s Manual Line Status Register reserved Description...
Page 376: Mcr Bit Definitions
• DTR = 1 forces DSR to a 1 • RTS = 1 forces CTS to a 1 • OUT1 = 1 forces RI to a 1 • OUT2= 1 forces DCD to a 1 Intel® PXA255 Processor Developer’s Manual UART...
Page 377: Modem Status Register (Msr)
The Interrupt Controller will still trigger interrupts if the pins are in Alternate Function Mode. Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IER[MIE] is set. This is a read-only. Ignore reads from reserved bits. Intel® PXA255 Processor Developer’s Manual Modem Control Register reserved...
Page 378: Msr Bit Definitions
1 – nDSR pin has changed state Delta Clear To Send: DCTS 0 – No change in nCTS pin since last read of MSR 1 – nCTS pin has changed state 10-20 Modem Status Register reserved Description Intel® PXA255 Processor Developer’s Manual UART...
Page 379: Spr Bit Definitions
If two stop bits are programmed, the second is included in this interval. • The most recent FIFO read was performed more than four continuous character times ago. Intel® PXA255 Processor Developer’s Manual Table 10-16, has no effect on the UART. It is intended as a scratchpad register...
Page 380: Transmit Interrupt
This prevents the DMAC from attempting to access the FIFOs while software clears the error. When all the errors in the receive FIFO are cleared, receive DMA requests are automatically enabled and can be generated when the trigger level is reached. 10-22 Intel® PXA255 Processor Developer’s Manual...
Page 381: Slow Infrared Asynchronous Interface
The IRDA module is managed through the UART to which it is attached. The ISR, shown in Table 10-17, controls IRDA functions. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual UARTs 10-23...
Page 382: Isr Bit Definitions
3/16 of a bit wide in the middle of every zero bit and send no pulses for bits that are ones. The pulse for each zero bit must occur, even for consecutive bits with no edge between them. 10-24 Infrared Selection Register reserved Description Intel® PXA255 Processor Developer’s Manual UART...
Page 383: Ir Transmit And Receive Example
Note: Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set. Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in Intel® PXA255 Processor Developer’s Manual START START shows an asynchronous transmission as it is sent from the UART.
Page 384: Ffuart Register Summary
BTRBR BTTHR BTIER BTIIR BTFCR BTLCR BTMCR BTLSR BTMSR Intel® PXA255 Processor Developer’s Manual Description Receive Buffer register (read only) Transmit Holding register (write only) IER (read/write) Interrupt ID register (read only) FCR (write only) LCR (read/write) MCR (read/write) LSR (read only)
Page 385: Stuart Register Summary
Table 10-20. STUART Register Summary Register Addresses 0x4070_0000 0x4070_0000 0x4070_0004 0x4070_0008 0x4070_0008 0x4070_000C 0x4070_0010 0x4070_0014 0x4070_0018 0x4070_001C 0x4070_0020 0x4070_0000 0x4070_0004 Intel® PXA255 Processor Developer’s Manual DLAB Bit Name Value BTSPR BTISR BTDLL BTDLH DLAB Bit Name Value STRBR STTHR STIER STIIR...
Page 386: Uart Register Differences
Table 10-21. Flow Control Registers in BTUART and STUART Bit7-5 BTMCR reserved BTMSR reserved STMCR reserved 10-28 Bit4 Bit3 Bit2 LOOP OUT2 reserved reserved reserved LOOP OUT2 reserved Intel® PXA255 Processor Developer’s Manual Table 10-21. Bit1 Bit0 reserved reserved DCTS reserved reserved...
Page 387: Ficp Signal Description
Fast Infrared Communication Port The Fast Infrared Communications Port (FICP) for the PXA255 processor operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The FICP is based on the 4-Mbps IrDA standard and uses four- position pulse modulation (4PPM) and a specialized serial packet protocol developed for IrDA transmission.
Page 388: Ppm Modulation Encodings
Receive data sample counter frequency = 6/pulse width. Each timeslot is sampled on the third clock. 11-2 Chip Timeslots Nibble 3 Nibble 2 Nibble 0 Nibble 1 Intel® PXA255 Processor Developer’s Manual Figure 11-2 shows Nibble 1 Nibble 0 Nibble 2 Nibble 3 125 ns...
Page 389: Frame Format
If a data field that is not a multiple of eight bits is received, an abort is signalled. Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port Figure...
Page 390: Crc Field
11-4 x 32 x 26 x 23 x 22 x 16 x 12 Figure 11-2). The chips are synchronized during the reception Intel® PXA255 Processor Developer’s Manual x 11 x 10...
Page 391: Transmit Operation
CPU or DMA to fill the FIFO after the FICP is enabled. When the FICP is enabled, the transmit logic issues a service request if its FIFO requires more data. Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port 11-5...
Page 392: Transmit And Receive Fifos
The transmit FIFO is 128 entries deep and 8 bits wide. The receive FIFO is 128 entries deep, 11 bits wide. The receive FIFO uses 3 bits of its entries as status bits. The transmit FIFO and the receive FIFO use two separate, dedicated DMA requests. 11-6 Intel® PXA255 Processor Developer’s Manual...
Page 393: Trailing Or Error Bytes In The Receive Fifo
Each of these hardware-detected events signals an interrupt request to the interrupt controller. The status registers also contain flags for transmitter busy, receiver synchronized, receive FIFO not empty, and transmit FIFO not full (no interrupt generated). Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port 11-7...
Page 394: Ficp Control Register 0 (Iccr0)
Table 11-2, contains eight valid bit fields that control various functions for Fast Infrared Communication Port Control Register 0 (ICCR0) reserved Description address is recognized or address is the broadcast address. Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port...
Page 395 1 = Output of transmit serial shifter is connected to input of receive serial shifter. IrDA transmission. 0 = ICP unit is not enabled. 1 = ICP unit is enabled. Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port Control Register 0 (ICCR0) reserved Description transmit underrun interrupt generation.
Page 396: Ficp Control Register 1 (Iccr1)
The broadcast address 0xFF in the incoming frame always generates a match. 11-10 Table 11-3, contains the 8-bit address match value field that the FICP uses to Fast Infrared Communication Port Control Register 1 (ICCR1) reserved Description Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port...
Page 397: Ficp Control Register 2 (Iccr2)
0b01- receive FIFO service request is generated when the FIFO has 16 bytes or more 0b10- receive FIFO service request is generated when the FIFO has 32 bytes or more 0b11- reserved Intel® PXA255 Processor Developer’s Manual Table 11-4, contains two bit fields that control the polarity of the transmit...
Page 398: Ficp Data Register (Icdr)
Write - Place data at end of transmit FIFO 11-12 Table 11-5, is a 32-bit register and its lower 8 bits are the top entry of the Fast Infrared Communication Port Data Register (ICDR) reserved Description Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port DATA...
Page 399: Ficp Status Register 0 (Icsr0)
0 = Transmit FIFO has more than 96 entries of data or transmitter disabled. 1 = Transmit FIFO has 96 or less entries of data and transmitter is enabled. DMA service Intel® PXA255 Processor Developer’s Manual Table 11-6, contains bits that signal the transmit FIFO service request,...
Page 400 Status Register 0 (ICSR0) reserved Description pulses or any invalid chips were detected on the receive pin. EOF bit set on last piece of “good” data received before the abort, interrupt requested. Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port...
Page 401: Ficp Status Register 1 (Icsr1)
0 = Receiver is in hunt mode or is disabled. 1 = Receiver logic is synchronized with the incoming data (no interrupt generated). Intel® PXA255 Processor Developer’s Manual 11-7, contains flags that indicate that the receiver is synchronized, the Fast Infrared Communication Port...
Page 402: Ficp Register Summary
0x4080_0018 11-16 Name Description ICCR0 FICP control register 0 ICCR1 FICP control register 1 ICCR2 FICP control register 2 ICDR FICP data register — reserved ICSR0 FICP status register 0 ICSR1 FICP status register 1 Intel® PXA255 Processor Developer’s Manual...
Page 403: Usb Device Controller
USB Device Controller This section describes the Universal Serial Bus (USB) protocol and its implementation-specific options for device controllers for the PXA255 processor. These options include endpoint number, type, and function; interrupts to the core; and a transmit/receive FIFO interface. A working knowledge of the USB standard is vital to using this section effectively.
Page 404: Device Configuration
FIFO Size (bytes) X Type Function number of FIFOs Control IN/OUT Bulk 64x2 Bulk 64x2 Isochronous 256x2 Isochronous 256x2 Interrupt Bulk 64x2 Bulk 64x2 Isochronous 256x2 Isochronous 256x2 Interrupt Bulk 64x2 Bulk 64x2 Isochronous 256x2 Isochronous 256x2 Interrupt Intel® PXA255 Processor Developer’s Manual...
Page 405: Signalling Levels
A zero is represented by a transition, and a one is represented by no transition, which produces the data. Each time a zero occurs, the receiver logic synchronizes the baud clock to the Intel® PXA255 Processor Developer’s Manual UDC+/UDC- Pin Levels UDC+ high, UDC- low (same as a 1).
Page 406: Field Formats
When the UDC detects a packet that is addressed to it, it uses the Endpoint field to determine which of the UDC’s endpoints is being addressed. The Endpoint field contains four bits. Encodings for endpoints 0 (0000b) through 15 (1111b) are allowed. The Endpoint field follows the Address field. 12-4 Intel® PXA255 Processor Developer’s Manual...
Page 407: Packet Formats
CRC5 field (see 1 ms prevents the UDC from entering Suspend mode. Table 12-4. SOF Token Packet Format 8 bits Sync Intel® PXA255 Processor Developer’s Manual +1) called CRC16. For both CRCs, the checker 8 bits 7 bits 4 bits...
Page 408: Transaction Formats
8 bits 0–1023 bytes Data Table 12-6 8 bits Table 12-7. Packets sent from the UDC to the host are highlighted in Intel® PXA255 Processor Developer’s Manual Table 12-5). The UDC supports 16 bits CRC16 shows the format of a handshake...
Page 409: Isochronous Transaction Formats
Action UDC successfully received control from host UDC temporarily unable to receive data UDC endpoint needs host intervention UDC detected PID, CRC, or bit stuff error Intel® PXA255 Processor Developer’s Manual USB Device Controller Token Packet Data Packet DATA0/DATA1 None...
Page 410: Udc Device Requests
Refer to the Universal Serial Bus Specification Revision 1.1 for a full description of host device requests. 12-8 Token Packet Data Packet DATA0 None None DATA0 Packets from UDC to host are boldface Intel® PXA255 Processor Developer’s Manual Figure 12-10 Handshake Packet STALL None...
Page 411: Configuration
128 bytes maximum packet Isochronous OUT data, the UDC recognizes the end of the packet, sets UDCCS4[RPC], and an interrupt is generated. Intel® PXA255 Processor Developer’s Manual Name Enables a specific feature such as device remote wake-up or endpoint stalls.
Page 412: Udc Hardware Connection
5 V. This solution does not reduce signal bounce, so software must compensate by reading the GPIO repeatedly until it proves to be stable. A third solution is a signal bounce minimization circuit that can tolerate 5 V but produces a 3.3 V signal to the GPIO pin. 12-10 Intel® PXA255 Processor Developer’s Manual...
Page 413: Self-Powered Device
During sleep, the USB controller is in reset and does not respond to the host PC. When it returns from sleep mode, the peripheral does not respond to its host-assigned address. Intel® PXA255 Processor Developer’s Manual 5 V to 3.3 V 470K 1.5K...
Page 414: Bus-Powered Devices
UDCCS0[IPR] to send a zero-length packet without loading data in the FIFO. After it sends the zero-length packet, software sets the internal state machine to EP0_END_XFER. 12-12 until all the data is transmitted or the last data packet is a short packet. Intel® PXA255 Processor Developer’s Manual...
Page 415: Case 2: Ep0 Control Read With A Premature Status Stage
UDCCS0[FTF] bit to clean up any buffer pointers and empty the transmit FIFO. Intel® PXA255 Processor Developer’s Manual until all the data is transmitted or the last data packet is a short packet. are repeated, the host sends a premature STATUS OUT stage, which...
Page 416: Case 3: Ep0 Control Write With Or Without A Premature Status Stage
If 12-14 are repeated until all of the data is received. are repeated, the host sends a STATUS IN stage, which indicates that Intel® PXA255 Processor Developer’s Manual...
Page 417: Case 4: Ep0 No Data Command
• Enable the EP1 interrupt to allow the Megacell to directly handle the transaction. 12.5.5.1 Software Enables the DMA If software enables the DMA engine, use the following steps: Intel® PXA255 Processor Developer’s Manual USB Device Controller 12-15...
Page 418: Case 6: Ep2 Data Receive (Bulk-Out)
If the packet size is less than 32 bytes, software uses interrupt mode. 12-16 repeat until all the bulk data is sent to the host PC. repeat until all of the data is sent to the host PC. Intel® PXA255 Processor Developer’s Manual...
Page 419: Case 7: Ep3 Data Transmit (Isochronous-In)
Enable the SOF interrupt to handle the transaction on a frame count basis. 12.5.7.1 Software Enables DMA If software enables the DMA engine to handle the transaction: Intel® PXA255 Processor Developer’s Manual repeat until all the data has been read from the host. USB Device Controller 12-17...
Page 420: Case 8: Ep4 Data Receive (Isochronous-Out)
12-18 repeat until all the data has been sent to the host. repeat until all of the data is sent to the host PC. repeat until all the data is sent to the host PC. Intel® PXA255 Processor Developer’s Manual...
Page 421 3. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet. 4. If UDCCS4[RNE] is set, software uses the UDCWC4 count register to read the proper amount of data from the EP4 data FIFO (UDDR4). 5. Software clears the UDCCS4[RPC] bit. Intel® PXA255 Processor Developer’s Manual USB Device Controller 12-19...
Page 422: Case 9: Ep5 Data Transmit (Interrupt-In)
UDCCR[REM] bit. 12-20 repeat until all the data has been read from the host. repeat until all the data is sent to the host PC. repeat until all the data is sent to the host PC. Intel® PXA255 Processor Developer’s Manual...
Page 423: Case 11: Suspend Interrupt
UDC. A status register indicates the state of the interrupt sources. Each of the sixteen endpoints (control, OUT, and IN) have a control or status register. Endpoint 0 (control) has an Intel® PXA255 Processor Developer’s Manual USB Device Controller...
Page 424: Udc Control Register (Udccr)
All entries in the transmit and receive FIFO are also reset. 12-22 Table 12-12, contains seven control bits: one to enable the UDC, one to show UDCCR reserved Description Intel® PXA255 Processor Developer’s Manual Read/Write and Read-Only...
Page 425 The UDE bit is cleared to zero, which disables the UDC following a Megacell reset. Writes to reserved bits are ignored and reads return zeros. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual USB Device Controller 12-23...
Page 426: Udc Control Function Register (Udccfr)
(B-step default) 1 = Send NAK response to SET_CONFIGURATION and SET_INTERFACE commands until UDCCFR[AREN] = 1 This bit must be set to 1. 0 = Reserved 1 = Must be configured to 1. Intel® PXA255 Processor Developer’s Manual USB Device Controller...
Page 427: Udc Endpoint 0 Control/Status Register (Udccs0)
0 FIFO to be transmitted. The core must not set this bit if a max_packet is to be transmitted. The UDC clears this bit when the packet has been successfully transmitted, the Intel® PXA255 Processor Developer’s Manual Table...
Page 428 IN transmission or the reception of a control OUT, the USIR0[IR0] bit in the UDC interrupt register is set if the endpoint 0 interrupt is enabled via UICR0[IM0]. The Intel XScale® microarchitecture is not able to clear UDCCS0[IPR] and always reads back a zero...
Page 429: Udc Endpoint X Control/Status Register (Udccs1/6/11)
TFS is cleared when two complete packets of data remain in the FIFO. A complete packet of data is signified by loading 64 bytes of data or by setting UDCCSx[TSP]. Intel® PXA255 Processor Developer’s Manual Table 12-15, contains 6 bits that are used to operate endpoint(x), a Bulk...
Page 430 Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCSx[FTF] bit. 12.6.4.7 Bit 6 Reserved Bit 6 is reserved for future use. 12-28 Intel® PXA255 Processor Developer’s Manual...
Page 431: Udc Endpoint X Control/Status Register (Udccs2/7/12)
Receive FIFO service (read-only). 0 = Receive FIFO has less than 1 data packet. 1 = Receive FIFO has 1 or more data packets. Intel® PXA255 Processor Developer’s Manual Table 12-16, contains 7 bits that are used to operate endpoint x, a Bulk...
Page 432 UDCCSx[SST] bit is set. To ensure that no data is transmitted after the Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCSx[FTF] bit. 12-30 Intel® PXA255 Processor Developer’s Manual...
Page 433: Udc Endpoint X Control/Status Register (Udccs3/8/13)
0 = Transmit FIFO has no room for new data 1 = Transmit FIFO has room for at least 1 complete data packet Intel® PXA255 Processor Developer’s Manual Table 12-17, contains 4 bits that are used to operate endpoint(x), an...
Page 434: Udc Endpoint X Control/Status Register (Udccs4/9/14)
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. 12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14) UDCCS4/9/14, shown in Isochronous OUT endpoint. 12-32 Table 12-18, contains six bits that are used to operate endpoint(x), an Intel® PXA255 Processor Developer’s Manual...
Page 435: Udccs4/9/14 Bit Definitions
The receive overflow bit generates an interrupt on IRx in the appropriate UDC status/interrupt register to alert the software that Isochronous data packets are being dropped because neither FIFO buffer has room for them. This bit is cleared by writing a 1 to it. Intel® PXA255 Processor Developer’s Manual UDCCS4 UDCCS9...
Page 436: Udc Endpoint X Control/Status Register (Udccs5/10/15)
Transmit short packet (read/write 1 to set). 1 = Short packet ready for transmission. — reserved 12-34 Table 12-19 contains 6 bits that are used to operate endpoint(x), an UDCCS5 UDCCS5 UDCCS15 reserved Description Intel® PXA255 Processor Developer’s Manual USB Device Controller...
Page 437 The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE. The bit’s read value is zero. Intel® PXA255 Processor Developer’s Manual UDCCS5 UDCCS5...
Page 438: Udc Interrupt Control Register 0 (Uicr0)
0 - 7. All of the UICR0 bits are reset to a 1 so interrupts are not generated on initial system reset. 12-36 12-20, contains 8 control bits to enable/disable interrupt service requests Intel® PXA255 Processor Developer’s Manual...
Page 439: Uicr0 Bit Definitions
It only blocks future zero to one transitions of the interrupt bit. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual UICR0 reserved...
Page 440: Udc Interrupt Control Register 1 (Uicr1)
It only blocks future zero to one transitions of the interrupt bit. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. 12-38 12-21, contains 8 control bits to enable/disable interrupt service requests UICR1 reserved Description Intel® PXA255 Processor Developer’s Manual USB Device Controller...
Page 441: Udc Status/Interrupt Register 0 (Usir0)
The interrupt request bit is set if the IM1 bit in the UDC interrupt control register is cleared and the IN packet complete (TPC) in UDC endpoint 1 control/status register is set. The IR1 bit is cleared by writing a 1 to it. Intel® PXA255 Processor Developer’s Manual 12-22, and USIR1, shown in Table...
Page 442 OUT packet ready bit (RPC) in the UDC endpoint 7 control/status register is set. The IR7 bit is cleared by writing a 1 to it. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 12-40 Intel® PXA255 Processor Developer’s Manual...
Page 443: Udc Status/Interrupt Register 1 (Usir1)
The interrupt request bit is set if the IM10 bit in the UDC interrupt control register is cleared and the IN packet complete (TPC) or in UDC endpoint 10 control/status register is set. The IR10 bit is cleared by writing a 1 to it. Intel® PXA255 Processor Developer’s Manual USIR1 reserved...
Page 444: Udc Frame Number High Register (Ufnhr)
UFNHR, shown in contained in the last received SOF packet, the isochronous OUT endpoint error status, and the SOF interrupt status/interrupt mask bit. 12-42 Table 12-24, holds the three most significant bits of the frame number Intel® PXA255 Processor Developer’s Manual...
Page 445: Ufnhr Bit Definitions
SOF interrupt and reads the frame number. This bit is not set if the token packet is corrupted or if the sync or PID fields of the data packet are corrupted. Intel® PXA255 Processor Developer’s Manual UFNHR reserved...
Page 446: Udc Frame Number Low Register (Ufnlr)
12-44 Table 12-25, is the eight least significant bits of the 11-bit frame number UFNLR reserved Description Table 12-26, maintains the remaining byte count in the active buffer Intel® PXA255 Processor Developer’s Manual USB Device Controller 8-Bit Frame Number LSB...
Page 447: Udc Endpoint 0 Data Register (Uddr0)
0 FIFO is after a valid command from the host is received and it requires a transmission in response. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual UBCR2 UBCR4...
Page 448: Udc Endpoint X Data Register (Uddr1/6/11)
UDDR6 UDDR11 reserved Description Table 12-29, is a double-buffered bulk OUT endpoint that is 64 bytes Intel® PXA255 Processor Developer’s Manual USB Device Controller Bottom of Endpoint 0 FIFO (for Reads) Top of Endpoint 0 FIFO (for Writes) USB Device Controller...
Page 449: Udc Endpoint X Data Register (Uddr3/8/13)
OUT packet to Endpoint(x). This NAK condition remains in place until a full packet space is available in the UDC at Endpoint(x). These are read-only registers. Ignore reads from reserved bits. Intel® PXA255 Processor Developer’s Manual UDDR2 UDDR7 UDDR12...
Page 450: Udc Endpoint X Data Register (Uddr5/10/15)
UDDR10 UDDR15 reserved Description Name UDCCR UDC Control Register — reserved for future use UDCCFR UDC Control Function Register — reserved for future use Intel® PXA255 Processor Developer’s Manual USB Device Controller 8-bit Data USB Device Controller 8-bit Data Description...
Page 451: Usb Device Controller
0x4060_0080 0x4060_0100 0x4060_0180 0x4060_0200 0x4060_0400 0x4060_00A0 0x4060_0600 0x4060_0680 0x4060_0700 0x4060_0900 Intel® PXA255 Processor Developer’s Manual Name Description UDCCS0 UDC Endpoint 0 Control/Status Register UDCCS1 UDC Endpoint 1 (IN) Control/Status Register UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register UDCCS3 UDC Endpoint 3 (IN) Control/Status Register...
Page 452 UDC Endpoint 10 Data Register UDDR11 UDC Endpoint 11 Data Register UDDR12 UDC Endpoint 12 Data Register UDDR13 UDC Endpoint 13 Data Register UDDR14 UDC Endpoint 14 Data Register UDDR15 UDC Endpoint 15 Data Register Intel® PXA255 Processor Developer’s Manual...
Page 453: Ac'97 Controller Unit
AC’97 Controller Unit 13.1 Overview The AC’97 Controller Unit (ACUNIT) of the PXA255 processor supports the AC’97 revision 2.0 features listed in Section link is a serial interface for transferring digital audio, modem, mic-in, CODEC register control, and status information.
Page 454: Signal Description
48 kHz frame indicator and synchronizer. Serial audio output data to CODEC for digital-to-analog conversion. Serial audio input data from Primary CODEC. Serial audio input data from Secondary CODEC. Intel® PXA255 Processor Developer’s Manual Table 13-7 for details on programing the...
Page 455: Ac-Link Digital Serial Interface Protocol
Table 13-2. Supported Data Stream Formats (Sheet 1 of 2) Channel PCM Playback PCM Record data CODEC control CODEC status Modem Line CODEC Output Modem Line CODEC Input Intel® PXA255 Processor Developer’s Manual AC-link nACRESET SDATA_OUT SYNC (48 kHz) SDATA_IN_0 SDATA_IN_1 BITCLK (12.288 MHz) Slots Comments...
Page 456: Ac-Link Audio Output Frame (Sdata_Out)
One input slot Data is returned on every frame. MDM CDC RSRVD DATA LEFT RIGHT STATUS MDM CDC DATA LEFT RIGHT Data Phase Intel® PXA255 Processor Developer’s Manual RSRVD RSRVD RSRVD RSRVD RSRVD I/O control RSRVD RSRVD RSRVD RSRVD RSRVD I/O Status...
Page 457: Start Of Audio Output Frame
DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit). Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and right sample stream time slots are filled with identical data. Intel® PXA255 Processor Developer’s Manual 20.8uS (48 KHz) slot(12) "0"...
Page 458 4. Specify the read/write direction of the access (slot 1, bit 19). 5. Specify the index to the CODEC register (slot 1, bits 18-12) 6. If the access is a write, write the data to the command data port (slot 2, bits 19-4). 13-6 Intel® PXA255 Processor Developer’s Manual...
Page 459: Slot 1 Bit Definitions
Slot 3 contains the composite digital audio left playback stream. If the playback stream contains an audio sample with a resolution that is less than 20 bits, the ACUNIT fills all trailing non-valid bit positions with zeroes. Intel® PXA255 Processor Developer’s Manual Description 1 = read, 0 = write...
Page 460: Ac-Link Audio Input Frame (Sdata_In)
When the “CODEC is ready” state is sampled, the next 12 sampled bits indicate which of the 12 time slots are assigned to input data streams and whether they contain valid data. Figure 13-5, “AC’97 Input Frame” 13-8 illustrates the time slot-based AC-link protocol. Intel® PXA255 Processor Developer’s Manual...
Page 461: Start Of An Audio Input Frame
When the AC-link CODEC Ready indicator bit is a one, the AC-link and AC’97 control and status registers are fully operational. The ACUNIT must probe the CODEC Powerdown Control/Status register to determine which subsections are ready. Intel® PXA255 Processor Developer’s Manual 20.8uS (48 KHz) slot(12) "0"...
Page 462: Input Slot 1 Bit Definitions
Slot 3 request: PCM Left channel Slot 4 request: PCM Right channel Slot 5 request: Modem Line 1 Slot 6 request: NA Slot 7 request: NA Slot 8 request: NA Slot 9 request: NA 13-10 Intel® PXA255 Processor Developer’s Manual...
Page 463: Input Slot 2 Bit Definitions
Slot 6 contains an optional third PCM system-input channel available for dedicated use by a microphone. This input channel supplements a true stereo output to enable a more precise echo- cancellation algorithm for speakerphone applications. Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit Description...
Page 464: Ac-Link Low Power Mode
SDATA_IN to a logic low voltage level. The sequence follows the timing diagram shown in Figure 13-7. Figure 13-7. AC-link Powerdown Timing SYNC BITCLK SDATA_OUT SDATA_IN Note: BITCLK not to scale 13-12 Write to Data slot 12 prev. frame 0x26 slot 12 prev. frame Intel® PXA255 Processor Developer’s Manual...
Page 465: Waking Up The Ac-Link
NOTES: 1. After SDATA_IN goes high, SYNC must be held for a minimum of 1 2. The minimum SDATA_IN wake up pulse width is 1 3. BITCLK not to scale Intel® PXA255 Processor Developer’s Manual Figure Power Down Codec Sleep...
Page 466: Acunit Operation
ACUNIT FIFO data: The ACUNIT has two Transmit FIFOs for audio-out and modem-out and three receive FIFOs for audio-in, modem-in, and mic-in. Data enters the transmit FIFOs by writing to either the PCM Data Register (PCDR) or the Modem Data Register (MODR). 13-14 Section 13.8.3. Section 13.8.3.17 Intel® PXA255 Processor Developer’s Manual...
Page 467: Initialization
Note: When nACRESET is deasserted, a read to the CODEC Mixer register returns the type of hardware that resides in the CODEC. If the CODEC is not present or if the AC’97 is not supported, the Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit Section 13.3...
Page 468 AC’97 Controller Unit ACUNIT does not set the CODEC-ready bit, GCR[PCRDY] for the Primary CODEC or GCR[SCRDY] for the Secondary CODEC. 13-16 Intel® PXA255 Processor Developer’s Manual...
Page 469: Trailing Bytes
44.1 kHz. When the CODEC transmits data (ACUNIT-receive mode), it can use the same algorithm to transmit valid frames with some empty ones mixed in between. Intel® PXA255 Processor Developer’s Manual Table 13-8. Software clears this bit by writing a 1 to it.
Page 470: Functional Description
During receive over-run conditions, data that the CODEC sends is not recorded. 13-18 Figure 13-3. Table 13-11 Table 13-20 Table 13-12, Table 13-16, and Table 13-21 Intel® PXA255 Processor Developer’s Manual for details regarding the status bits. for details regarding the status...
Page 471: Interrupts
• Channel-specific audio ACUNIT registers refer to PCM-out, PCM-in, and mic-in channels. • Channel-specific Modem ACUNIT registers refer to modem-out and modem-in channels. • Audio CODEC registers • Modem CODEC registers Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit 13-19...
Page 472: Gcr Bit Definitions
1 = Enables an interrupt to occur when the Primary CODEC sends the CODEC READY bit — reserved 13-20 GCR Register reserved Description address and data to the CODEC. data to the CODEC. CODEC bit on the SDATA_IN_1 pin on the SDATA_IN_0 pin. Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit...
Page 473 1 = If this bit is set, the change in value of a GPI (as indicated by bit 0 of slot 12) causes an 13.8.3.2 Global Status Register (GSR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual GCR Register reserved Description...
Page 474: Gsr Bit Definitions
0 = None of the mic-in channel interrupts occurred. MINT 1 = One of the mic-in channel interrupts occurred. When the specific interrupt is cleared, this bit will be cleared (interruptible). 13-22 GSR Register Description Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit...
Page 475: Pocr Bit Definitions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset Bits Name 31:4 — reserved Intel® PXA255 Processor Developer’s Manual GSR Register Description new values are available in slot 12. POCR Register reserved Description AC’97 Controller Unit...
Page 476: Picr Bit Definitions
0 = No interrupt will occur even if bit 4 in the PISR is set 1 = An interrupt will occur if bit 4 in the PISR is set. — reserved 13-24 POCR Register reserved Description PICR Register reserved Description Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit AC’97 Controller Unit...
Page 477: Posr Bit Definitions
1 = A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this FIFOE Bit is cleared by writing a 1 to this bit position. — reserved Intel® PXA255 Processor Developer’s Manual POSR Register reserved Description this case, the last valid sample is repetitively sent out and the pointers are not incremented.This could happen due to:...
Page 478: Pcdr Bit Definitions
CODEC IO cycle after having read this bit. the currently accessing driver must try again later. (This bit applies to all CODEC IO cycles - GPIO or otherwise). PCDR Register Description Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit AC’97 Controller Unit PCM_LDATA...
Page 479: Pcm Transmit And Receive Operation
1 = An interrupt will occur if bit 4 in the MCSR is set. — reserved 13.8.3.10 Mic-In Status Register (MCSR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Write Processor/DMA Processor/DMA PCDR Register RxFIFO...
Page 480: Mcsr Bit Definitions
FIFO and will be lost. This could happen due to DMA controller having excessive bandwidth requirements and hence not being able to flush out the Receive FIFO in time. MCDR Register Description Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit AC’97 Controller Unit MIC_IN_DAT...
Page 481: Mocr Bit Definitions
1 = An interrupt will occur if bit 4 in the MOSR is set. — reserved 13.8.3.13 Modem-In Control Register (MICR) This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Receive Data RxEntry15 MCDR Register Mic-in Receive FIFO...
Page 482: Micr Bit Definitions
No more valid buffer data available for transmits. d. Buffer data available but DMA controller has excessive bandwidth requirements. Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit AC’97 Controller Unit...
Page 483: Misr Bit Definitions
MODEM_DAT Modem data A 32-bit sample write to this register updates the data into the Modem Transmit FIFO. A read to this register gets a 32-bit sample from the Modem Receive FIFO. Intel® PXA255 Processor Developer’s Manual MISR Register reserved...
Page 484 In the equations, Shift_Left_Once() shifts the 7-bit CODEC address left by one bit and shifts a 0 to the LSB. The address translations are shown in 13-32 Processor/DMA Processor DMA Write Read MODR Register 0x0000 Table 13-23. Intel® PXA255 Processor Developer’s Manual Receive Data RxEntry15 Modem Receive FIFO RxEntry3 RxEntry2 RxEntry1 RxEntry0...
Page 485: Address Mapping For Codec Registers
0x4050_0268 0x36 0x4050_026C 0x38 0x4050_0270 0x3A 0x4050_0274 0x3C 0x4050_0278 0x3E 0x4050_027C 0x40 0x4050_0280 0x42 0x4050_0284 Intel® PXA255 Processor Developer’s Manual Processor Processor Physical Physical Address for a Address for a Secondary Primary Audio CODEC Modem CODEC 0x4050_0300 0x4050_0400 0x4050_0304 0x4050_0404...
Page 486 0x4050_03E0 0x4050_04E0 0x4050_03E4 0x4050_04E4 0x4050_03E8 0x4050_04E8 0x4050_03EC 0x4050_04EC 0x4050_03F0 0x4050_04F0 0x4050_03F4 0x4050_04F4 0x4050_03F8 0x4050_04F8 0x4050_03FC 0x4050_04FC Intel® PXA255 Processor Developer’s Manual Processor Physical Address for a Secondary Modem CODEC 0x4050_0588 0x4050_058C 0x4050_0590 0x4050_0594 0x4050_0598 0x4050_059C 0x4050_05A0 0x4050_05A4 0x4050_05A8 0x4050_05AC 0x4050_05B0...
Page 487: Ac'97 Register Summary
(0x4050_0300 - 0x4050_03FC) with all in increments of 0x00004 (0x4050_0400 - 0x4050_04FC) with all in increments of 0x0000_0004 (0x4050_0500 - 0x4050_05FC) with all in increments of 0x00004 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit Name Description POCR PCM Out Control Register...
Page 488 AC’97 Controller Unit 13-36 Intel® PXA255 Processor Developer’s Manual...
Page 489: Overview
Inter-Integrated-Circuit Sound (I Controller S is a protocol for digital stereo audio. The I PXA255 processor controls the I for stereo audio. The I the same time. 14.1 Overview The I2SC consists of buffers, status and control registers, serializers, and counters for transferring...
Page 490: Inter-Integrated-Circuit Sound (I2S) Controller
= SYNC * 64 Left/Right identifier Serial audio output data to CODEC Serial audio input data from CODEC for details regarding the GAFR. Intel® PXA255 Processor Developer’s Manual Description Section 4.1.3.2, “GPIO Pin for details regarding the GPDR. Section 4.1.3.6, Section 14.6.1,...
Page 491: Controller Operation
1. Set the BITCLK direction by programming the SYSUNIT’s GPIO Direction register, the SYSUNIT’s GPIO Alternate Function Select register, and bit 2 of the I2SC’s Serial Audio Controller Global Control Register (SACR0). Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller for details regarding the GAFR.
Page 492: Disabling And Enabling Audio Replay
DREC bit of the SACR1 Register. For more details, see 14-4 S or MSB-Justified modes of operation. This can be done by S/MSB-Justified Control Register (SACR1). Section 14.6.2. Section 14.6.5. Intel® PXA255 Processor Developer’s Manual Section 14.6.3. Section 14.6.1.2, regarding Section 14.6.2.
Page 493: Transmit Fifo Errors
BITCLK and SYSCLK are configured as output pins, and both are supplied to the CODEC. If BITCLK is supplied by the CODEC, then it is configured as an input pin. In this case, the SYSCLK’s GPIO pin can be used for an alternate function. Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller Section 14.6.3,...
Page 494: Data Formats
16.000 kHz (closest std = 16.00 kHz) 2.836 MHz 708.92 kHz 11.077 kHz (closest std = 11.025 kHz) 2.048 MHz 512.00 kHz 8.000 kHz (closest std = 8.00 kHz) Intel® PXA255 Processor Developer’s Manual SYNC or Sampling frequency = BITCLK / 64...
Page 495: Msb-Justified Data Formats (16 Bits
Figure 14-2. MSB-Justified Data Formats (16 bits BITCLK SData_Out SYNC Note: Timing for SData_In is identical to SData_Out. Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller provide timing diagrams that show formats for I cycle0 13 14 15 16...
Page 496: Registers
BITCLK domain. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. 14-8 14-3, controls common I S functions. Intel® PXA255 Processor Developer’s Manual...
Page 497: Sacr0 Bit Definitions
Under normal operating conditions, the processor or the DMA controller can only write to the Transmit FIFO and only read the Receive FIFO. Programming these bits allows the processor or the DMA controller to read and write both FIFOs. Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller Serial Audio Controller Global...
Page 498: Serial Audio Controller I2S/Msb-Justified Control Register (Sacr1)
• I2SLINK can read the Transmit FIFO but cannot write to the Receive FIFO. Table 14-5 shows the recommended TFTH and RFTH # of FIFO entries TFTH Value S/MSB-Justified Control Register 14-6, specifically controls the I2S and MSB-Justified modes. Intel® PXA255 Processor Developer’s Manual RFTH Value...
Page 499: Serial Audio Controller I2S/Msb-Justified Status Register (Sasr0)
(RFL(3:0) == 4’b0) Actual_RFL(4:0) = {RNE, RFL(3:0)} else Actual_RFL(4:0) = {1’b0, RFL(3:0)} This is a read-only register. Ignore reads from reserved bits. Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller Serial Audio Controller I S/MSB- Justified Control Register...
Page 500: Serial Audio Clock Divider Register (Sadiv)
S attempted data read from an empty Transmit FIFO S Busy: S is idle or disabled S currently transmitting or receiving a frame 14-8, is used for generating six different BITCLK frequencies and hence Intel® PXA255 Processor Developer’s Manual S Controller S disabled S disabled...
Page 501: Serial Audio Interrupt Clear Register (Saicr)
Clear Receive FIFO overrun Interrupt and ROR status bit in SASR0. Clear Transmit FIFO under-run Interrupt and TUR status bit in SASR0. — reserved Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller Serial Audio Clock Divider Register reserved Description 14-9, is the Interrupt Control Register.
Page 502: Serial Audio Interrupt Mask Register (Saimr)
Serial Audio Interrupt Mask Register reserved Description Table 14-11, updates the data into the Transmit FIFO. Serial Audio Data Register Description Intel® PXA255 Processor Developer’s Manual Table 14-10, enables the S Controller 5 4 3 reserved 0 0 0 S Controller...
Page 503: Interrupts
All registers are word addressable (32 bits wide) and hence increment in units of 0x00004. All I2SC registers are mapped in the address range of 0x4040_0000 through 0x4040_0080, as shown Table 14-12. Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller Processor/DMA Write...
Page 504: Register Memory Map
SAIMR Serial Audio Interrupt Mask Register SAICR Serial Audio Interrupt Clear Register — reserved SADIV Audio clock divider register. See — reserved SADR Serial Audio Data Register (TX and RX FIFO access register). Intel® PXA255 Processor Developer’s Manual Section 14.4.
Page 505: Multimediacard Controller
15.1 Overview The PXA255 processor MultiMediaCard (MMC) controller acts as a link between the software used to access the processor and the MMC stack (a set of memory cards). The MMC controller is designed to support the MMC system, a low-cost data storage and communications system. A detailed description of the MMC system is available through the MMC Association’s web site at...
Page 506: Command Token Format
SPI mode. Block Data Description start bit data CRC7 end bit Description start byte data CRC16 Intel® PXA255 Processor Developer’s Manual Description start bit transmission bit command index argument CRC7 end bit Table 15-2 shows the...
Page 507: Mmc Mode Operation Without Data Token
MMCMD signal and the response and read data tokens are received on the MMDAT signal. a data token. Figure 15-5 respectively. Intel® PXA255 Processor Developer’s Manual Figure 15-2 while Figure 15-3 from host to card...
Page 508: Mmc Controller Functional Description
Response data from card to from card to Response Data Block data from host to from card to Data response Data Block Response Data Response Intel® PXA255 Processor Developer’s Manual from card to host Response Busy Next Command Command Busy...
Page 509 8-bit transmit FIFOs that are 32 entries deep. The registers and FIFOs are accessible by the software. The MMC controller also enables minimal data latency by buffering data and generating and checking CRCs. Refer to Section 15.4 for examples. Intel® PXA255 Processor Developer’s Manual 15-5...
Page 510: Mmc Signal Description
Chip Select 0 (used only in SPI mode) Output Chip Select 1 (used only in SPI mode) for a complete description of the GPIO alternate Section 2.6, “Reset” on page Intel® PXA255 Processor Developer’s Manual Description for a description of the process Section 4.1.2, 2-6. All registers...
Page 511 For read transfers, the stop transmission command may occur after the data transmission has occurred. There is no CRC protection for data in this mode. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller Table 15-1).
Page 512: Error Detection
Interrupts and masking are described in CMDAT[DMA_EN] bit will also mask the MMC_I_MASK[RXFIFO_RD_REQ] and MMC_I_MASK[TXFIFO_WR_REQ] interrupt bits. 15-8 Section 15.5.11 Section 15.5.12. The Intel® PXA255 Processor Developer’s Manual...
Page 513: Clock Control
Stopping the clock while data is in the transmit or receive FIFOs will cause unpredictable results. If the software stops the clock at any time, it must wait for the MMC_STAT[CLK_EN] status bit to be cleared before proceeding. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller 15-9...
Page 514: Data Fifos
The receive FIFO is readable on byte boundaries and the FIFO read request is only asserted once per FIFO access (once per 32 bytes available). Therefore, 32 bytes must be read for each request, except for the last read which may be less than 32 bytes. 15-10 Intel® PXA255 Processor Developer’s Manual...
Page 515 The transmit FIFO is writable on byte boundaries and the FIFO write request is only asserted once per FIFO access (once per 32 entries available). Therefore, 32 bytes must be written for each request, except for the last write which may be less than 32 bytes. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller 15-11...
Page 516: Card Communication Protocol
The CMDAT[DMA_EN] bit must be set to a 1 to enable communication with the DMA and it must be set to a 0 to enable program I/O. 15.3 Card Communication Protocol This section discusses the software’s responsibilities and the communication protocols used between the MMC and the card. 15-12 Intel® PXA255 Processor Developer’s Manual...
Page 517: Basic, No Data, Command And Response Sequence
• MMC_NOB After the software writes the registers and starts the clock, the software must read the MMC_RES as described above and read or write the MMC_RXFIFO or MMC_TXFIFO FIFOs. Intel® PXA255 Processor Developer’s Manual Section 15.4. Section 15.3.1. In addition, before starting the...
Page 518 The block length if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified. • The number of blocks to be transferred. 15-14 Intel® PXA255 Processor Developer’s Manual...
Page 519 The software must then stop the clock, write the registers for a stop transmission command, and then start the clock. At this point, the software must wait for the MMC_I_REG[DATA_TRAN_DONE] and MMC_I_REG[PRG_DONE] interrupts. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller × Section 15.3.2.1.
Page 520: Stream Data Read
If the software disconnects a card while it is in a busy state, the busy signal will be turned off and the software can connect a different card. The software may not start another command sequence on the same card while the card is busy. 15-16 Section 15.3.2.2. Intel® PXA255 Processor Developer’s Manual...
Page 521: Spi Functionality
To communicate with a card in SPI mode, the software must set the MMC_SPI register as follows: 1. MMC_SPI[SPI_EN] must be set to 1. 2. MMC_SPI[SPI_CS_EN] must be set to 1. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller Section 15.3.1.
Page 522: No Data Command And Response Sequence
15.4.4. These registers must be set before the clock is started: • Set MMC_NOB register to 0x0001. • Set MMC_BLKLEN to the number of bytes per block. 15-18 Section 15.4.1. Section 15.4.1. Section 15.4.4 with the following additions: the Intel® PXA255 Processor Developer’s Manual...
Page 523: Single Block Read
MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state. 15.4.7 Single Block Read In a single block read command, the software must stop the clock and set the registers as described Section 15.4.4. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller Section 15.4.4. 15-19...
Page 524: Multiple Block Write
The multiple block read mode requires a stop transmission command, CMD12, after the data from the card is received. After the MMC_I_REG[DATA_TRAN_DONE] interrupt has occurred, the software must program the controller registers to send a stop data transmission command. 15-20 Section 15.4.4. Intel® PXA255 Processor Developer’s Manual...
Page 525: Stream Write
In a stream read command, the software must stop the clock and set the registers as described in Section 15.4.4. These registers must be set before the clock is turned on: • Set MMC_NOB register to ffffh. Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller Section 15.4.4. Section 15.4.4.
Page 526: Mmc Controller Registers
Reads from this register are unpredictable. This is a write-only register. Write zeros to reserved bits. 15-22 Section 15.4.4. Table 15-23 describe the registers and FIFOs. Table 15-5, allows the software to start and stop the MMC bus Intel® PXA255 Processor Developer’s Manual Section 15.4.4.
Page 527: Mmc_Status Register (Mmc_Stat)
Program Done PRG_DONE Data Transmission Done DATA_TRAN_ DONE 10:9 — reserved Intel® PXA255 Processor Developer’s Manual MMC_STRPCL Register reserved Description Table 15-6, is the status register for the MMC controller. The register is MMC_STAT Register Description 0 – Command and response sequence has not completed 1 –...
Page 528: Mmc_Clkrt Register (Mmc_Clkrt)
1 – Card response timed out 0 – Card read data has not timed out 1 – Card read data timed out Table 15-7, specifies the frequency division of the MMC bus clock. The Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller...
Page 529: Mmc_Spi Register (Mmc_Spi)
Specifies the relative address of the card to activate the SPI CS SPI_CS_ADD RESS SPI Chip Select Enable SPI_CS_EN CRC Generation Enable CRC_ON Intel® PXA255 Processor Developer’s Manual MMC_CLKRT Register reserved Description Table 15-8, is for SPI mode only and is set by the software. MMC_SPI Register...
Page 530: Mmc_Cmdat Register (Mmc_Cmdat)
MMC_CMDAT Register reserved Description 0 – Program I/O mode 1 – DMA mode 0 – Do not precede command sequence with 80 clocks 1 – Precede command sequence with 80 clocks Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller MultiMediaCard Controller...
Page 531: Mmc_Resto Register (Mmc_Resto)
Name 31:7 — reserved RES_TO Number of MMC clocks before a response time-out Intel® PXA255 Processor Developer’s Manual MMC_CMDAT Register reserved Description 0 – Data transfer of the current command sequence is not in stream mode 1 – Data transfer of the current command sequence is in stream mode 0 –...
Page 532: Mmc_Rdto Register
Specifies the length of time before a data read time-out 15-28 Table 15-11, determines the length of time that the controller waits after a × MMC_RDTO[READ_TO] 20MHz MMC_RDTO Register Description Intel® PXA255 Processor Developer’s Manual × MMC_RDTO[READ_TO] ----------------------------------------------------------------------------------------- - sec MultiMediaCard Controller READ_TO...
Page 533: Mmc_Blklen Register (Mmc_Blklen)
Bits Name 31:16 — reserved 15:0 MMC_NOB Number of blocks for a multiple block transfer Intel® PXA255 Processor Developer’s Manual Table 15-12, specifies the number of bytes in a block of data. MMC_BLKLEN Register reserved Description Table 15-13, specifies the number of blocks.
Page 534: Mmc_Prtbuf Register (Mmc_Prtbuf)
Buffer is partially full and must be swapped to the other transmit buffer Table 15-15, masks off the various interrupts when set to a 1. MMC_I_MASK Register reserved Description 0 – Not masked 1 – Masked Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller MultiMediaCard Controller...
Page 535: Mmc_I_Reg Register (Mmc_I_Reg)
MMC_CMDAT register. The software is responsible for monitoring these bits in program I/O mode. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual MMC_I_MASK Register reserved Description 0 –...
Page 536: Mmc_I_Reg Bit Definitions
0 – Card has not finished programming and is busy 1 – Card has finished programming and is no longer busy 0 – Data transfer is not complete 1 – Data transfer has completed or a read data time-out has occurred Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller...
Page 537: Command Index Values
001101 CMD13 001110 CMD14 001111 CMD15 010000 CMD16 010001 CMD17 010010 CMD18 010011 CMD19 Intel® PXA255 Processor Developer’s Manual Table 15-17, specifies the command number. MMC_CMD Register reserved Description Table 15-18) MODE ABBREVIATION MMC/SPI GO_IDLE_STATE MMC/SPI SEND_OP_COND ALL_SEND_CID SET_RELATIVE_ADDR SET_DSR...
Page 538 MMC/SPI TAG_SECTOR_START MMC/SPI TAG_SECTOR_END MMC/SPI UNTAG_SECTOR MMC/SPI TAG_ERASE_GROUP_START MMC/SPI TAG_ERASE_GROUP_END MMC/SPI UNTAG_ERASE_GROUP MMC/SPI ERASE FAST_IO GO_IRQ_STATE reserved MMC/SPI LOCK_UNLOCK reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved MMC/SPI APP_CMD MMC/SPI GEN_CMD Intel® PXA255 Processor Developer’s Manual...
Page 539: Mmc_Argh Register (Mmc_Argh)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 reserved Reset Bits Name 31:16 — reserved 15:0 ARG_L Lower 16 bits of command argument Intel® PXA255 Processor Developer’s Manual MODE ABBREVIATION reserved READ_OCR CRC_ON_OFF reserved for manufacturer reserved for manufacturer reserved for manufacturer reserved for manufacturer Table...
Page 540: Mmc_Rxfifo, Fifo Entry
15-21, contains the response after a command. It is 16 bits wide MMC_RES FIFO Entry Description Table 15-22, consists of two dual FIFOs, where each FIFO is eight bits MMC_RXFIFO Entry reserved Description Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller RESPONSE_DATA MultiMediaCard Controller READ_DATA...
Page 541: Mmc Controller Registers
0x4110_0018 0x4110_001c 0x4110_0020 0x4110_0024 0x4110_0028 0x4110_002c 0x4110_0030 0x4110_0034 0x4110_0038 Intel® PXA255 Processor Developer’s Manual Table 15-23, consists of two dual FIFOs, where each FIFO is eight bits MMC_TXFIFO Entry reserved Description Name MMC_STRPCL Control to start and stop MMC clock...
Page 542 MultiMediaCard Controller Table 15-24. MMC Controller Registers (Sheet 2 of 2) Address 0x4110_003c 0x4110_0040 0x4110_0044 15-38 Name MMC_RES Response FIFO (read only) MMC_RXFIFO Receive FIFO (read only) MMC_TXFIFO Transmit FIFO (write only) Intel® PXA255 Processor Developer’s Manual Description...
Page 543: Network Ssp Serial Port
Network SSP Serial Port This chapter describes the signal definitions and operation of the Intel® PXA255 Processor Network Synchronous Serial Protocol (NSSP) serial port. The NSSP is configured differently than the SSPC. 16.1 Overview The NSSP is a synchronous serial interface that connects to a variety of external analog-to-digital (A/D) converters, telecommunication CODECs, and many other devices that use serial protocols for data transfer.
Page 544: Signal Description
16.4 Operation The SSP controller transfers serial data between the PXA255 processor and an external device through FIFOs. The PXA255 processor CPU initiates the transfers using programmed I/O or DMA bursts to and from memory. Separate transmit and receive FIFOs and serial data paths permit simultaneous transfers in both directions to and from the external device, depending on the protocols chosen.
Page 545: Trailing Bytes In The Receive Fifo
Note: The time-out interrupt must be enabled by setting SSCR1[TINTE]. 16.4.3 Data Formats Four pins transfer data between the PXA255 processor and external CODECs or modems. Although four serial-data formats exist, each has the same basic structure and in all cases the pins are used as follows: Intel®...
Page 546 Note: The serial clock (SSPSCLK), if driven by the SSP, toggles only while an active data transfer is underway, unless receive-without-transmit mode is enabled by setting SSCR1[RWOT] and the frame format is not Microwire*, in which case the SSPSCLK toggles regardless of whether 16-4 Intel® PXA255 Processor Developer’s Manual...
Page 547: Texas Instruments Synchronous Serial Frame* Protocol (Multiple Transfers)
(a block of transfers is a group of back-to-back continuous transfers). Figure 16-1. Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers) SSPSCLK SSPSFRM SSPTX SSPRX Intel® PXA255 Processor Developer’s Manual Figure 16-1 through shows the TI Synchronous Serial Protocol for a single transmitted frame. Bit[0] Bit[N] Bit[N-1]...
Page 548: Texas Instruments Synchronous Serial Frame* Protocol (Single Transfers)
Figure 16-4 protocol for a single transmitted frame. 16-6 Bit[N] Bit[N-1] Bit[1] Undefined Bit[N] Bit[N-1] Bit[1] 4 to 32 Bits shows one of the four possible configurations for the Motorola SPI* frame Intel® PXA255 Processor Developer’s Manual Bit[0] Bit[0] Undefined A9518-02...
Page 549: Motorola Spi* Frame Protocol (Single Transfers)
SSPSCLK continues to transition for the rest of the frame. It is then held in its inactive state for one-half of an SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame. Intel® PXA255 Processor Developer’s Manual Bit[0]...
Page 550: Motorola Spi* Frame Protocols For Spo And Sph Programming (Multiple Transfers)
(the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of 16-8 SPO=0 SPO=1 Bit[N] Bit[N-1] Bit[1] Undefined Bit[N] Bit[N-1] Bit[1] 4 to 32 Bits Intel® PXA255 Processor Developer’s Manual Bit[0] End of Transfer Data State Bit[0] Undefined A9652-01...
Page 551: Motorola Spi* Frame Protocols For Spo And Sph Programming (Single Transfers)
Figure 16-7 shows the National Semiconductor Microwire* frame protocol with eight-bit command words when back-to-back frames are transmitted. Semiconductor Microwire* frame protocol with eight-bit command words for a single transmitted frame. Intel® PXA255 Processor Developer’s Manual SPO=0 SPO=1 Bit[N] Bit[N-1]...
Page 552 Bit[N] Bit[0] Undefined Frame Protocol (single transfers) Bit[7] or End of Transfer Data Bit[0] Bit[15] 8 or 16-Bit Control Undefined Bit[N] Intel® PXA255 Processor Developer’s Manual Bit[1] Bit[0] Bit[N] Undefined A9653-01 State Undefined Bit[0] Undefined 4 to 32 Bits A9521-02...
Page 553: Programmable Serial Protocol (Multiple Transfers)
(when SCMODE = 2) SSPSCLK (when SCMODE = 3) SSPTXD SSPRXD SSPSFRM (when SFRMP = 1) SSPSFRM (when SFRMP = 0) Intel® PXA255 Processor Developer’s Manual for more information. Undefined Undefined Network SSP Serial Port Transfer Data State End of Transfer Data State...
Page 554: Programmable Serial Protocol (Single Transfers)
Serial clock mode (SSPSP[SCMODE]) Serial frame polarity (SSPSP[SFRMP]) Start delay (SSPSP[STRTDLY]) Dummy start (SSPSP[DMYSTRT]) Data size Intel® PXA255 Processor Developer’s Manual End of Transfer Data State Undefined A9522-02 Range Units 0 - Fall, Rise, Low 1 - Rise, Fall, Low —...
Page 555: Hi-Z On Ssptxd
SSPSCLK or SSPSFRM is configured as an input. 16.4.4 Hi-Z on SSPTXD The PXA255 processor NSSP supports placing SSPTXD into Hi-Z during idle times instead of driving SSPTXD. SSCR1[TTE] enables Hi-Z on SSPTXD. SSCR1[TTELP] controls when SSPTXD is placed into Hi-Z.
Page 556: Ti Ssp With Sscr[Tte]=1 And Sscr[Ttelp]=1
Bit[N] Bit[N-1] Bit[1] Undefined Bit[N] Bit[N-1] Bit[1] 4 to 32 Bits shows the pin timing for this mode. Intel® PXA255 Processor Developer’s Manual Bit[0] Bit[0] Undefined A9975-01 Section 16.4.3.2. Bit[0] Bit[0] Undefined A9976-01 Section 16.4.3.3.
Page 557: National Semiconductor Microwire With Sscr1[Tte]=1
If the SSP is a master to frame, SSPTXD is Hi-Z two clock edges after the clock edge that drives the LSB. This occurs even if the SSP is a master of clock and this clock edge does not appear on the SSPSCLK. Figure 16-16 Intel® PXA255 Processor Developer’s Manual Bit[7] or Bit[0] Bit[15]...
Page 558: Psp Mode With Sscr1[Tte]=1 And Sscr1[Ttelp]=0 (Master To Frame)
(when SCMODE = 2) SSPSCLK (when SCMODE = 3) SSPTXD SSPRXD SSPSFRM (when SFRMP = 1) SSPSFRM (when SFRMP = 0) 16-16 Undefined shows the pin timing for this mode. Undefined Intel® PXA255 Processor Developer’s Manual Undefined A9979-01 Undefined A9980-01...
Page 559: Fifo Operation
16.4.5.1 Using Programmed I/O Data Transfers The PXA255 processor can perform FIFO filling and emptying in response to an interrupt from the FIFO logic. Each FIFO has a programmable trigger threshold at which an interrupt is triggered. When the number of entries in the receive FIFO exceeds the value in SSCR1[RFT], an interrupt is generated (if enabled).
Page 560: Register Descriptions
Before enabling the SSP (via SSE) the desired values for this register must be set. These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits. 16-18 16-3, contains bit fields that control various functions within the SSP. Intel® PXA255 Processor Developer’s Manual...
Page 561: Sscr0 Bit Definitions
0b00 – Serial Peripheral Interface* 0b01 – TI Synchronous Serial Protocol* 0b10 – Microwire* 0b11 – Programmable Serial Protocol Intel® PXA255 Processor Developer’s Manual SSCR0 20 19 18 17 16 15 14 13 12 Description causes the SSPSCLK frequency to immediately change.
Page 562: Ssp Control Register 1 (Sscr1)
29-bit data 0b1101 30-bit data 0b1110 31-bit data 0b1111 32-bit data 16-4, contains bit fields that control various SSP functions. Before Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port 11 10 9 Description Data Size 0b0000 reserved, undefined 0b0001...
Page 563: Sscr1 Bit Definitions
TTELP EBCEI SCFR 27:26 — Intel® PXA255 Processor Developer’s Manual SSCR1 20 19 18 17 16 15 14 13 12 Description TRANSMIT HI-Z LATER PHASE: This bit modifies the behavior of TTE. It causes SSPTXD to become Hi-Z 1/2 phase (or one clock edge) later than normal.
Page 564: Ssp Programmable Serial Protocol Register (Sspsp)
SSSR[BUSY] remains active (set to 1) until software clears the RWOT bit. 0 – Transmit/Receive mode. 1 – Receive With Out Transmit mode. reserved 16-5, contains bit fields used to program the various programmable serial- Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port 11 10 9 Description...
Page 565: Sspsp Bit Definitions
(SSCR1[SFRMDIR] set), this bit indicates the polarity of the incoming frame signal. 0 – SSPSFRM is active low. 1 – SSPSFRM is active high. Intel® PXA255 Processor Developer’s Manual SSPSP 20 19 18 17 16 15 14 13 12 SFRMWDTH...
Page 566: Ssp Time Out Register (Ssto)
16-6,specifies the time-out value used to signal a period of SSTO 20 19 18 17 16 15 14 13 12 16-25, contains bit fields used for testing purposes only. Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port 11 10 9 SFRMDLY...
Page 567: Ssp Status Register (Sssr)
• Receiver time-out, • Receive FIFO overrun, • Receive FIFO request • Transmit FIFO request. Intel® PXA255 Processor Developer’s Manual SSITR reserved Name — reserved TEST RECEIVE FIFO OVERRUN: 0 – No receive FIFO overrun service request is generated. TROR 1 –...
Page 568: Sssr Bit Definitions
1 – Attempted read from the transmit FIFO when the FIFO was empty, request interrupt. — reserved 16-26 SSSR 20 19 18 17 16 15 14 13 12 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port 11 10 9 Description...
Page 569 0 – Receive FIFO level exceeds RFT trigger threshold or the SSP is disabled 1 – Receive FIFO level is at or above RFT trigger threshold, request Interrupt Intel® PXA255 Processor Developer’s Manual SSSR 20 19 18 17 16 15 14 13 12...
Page 570: Ssp Data Register (Ssdr)
FIFO. The other register is temporary storage for data coming in through the receive FIFO. 16-28 SSSR 20 19 18 17 16 15 14 13 12 16-9, is a single address location that read and write data transfers access. Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port 11 10 9 Description...
Page 571: Network Ssp Serial Port Register Summary
Table 16-10. NSSP Register Address Map Physical Address 0x4140_0000 0x4140_0004 0x4140_0008 0x4140_000C 0x4140_0010 0x4140_0028 0x4140_002C Intel® PXA255 Processor Developer’s Manual SSDR 20 19 18 17 16 15 14 13 12 DATA Description Name NSSCR0 NSSP Control register 0 NSSCR1 NSSP Control register 1...
Page 572 Network SSP Serial Port 16-30 Intel® PXA255 Processor Developer’s Manual...
Page 573: Hardware Uart
Hardware UART This chapter describes the signal definitions and operations of the PXA255 processor hardware UART (HWUART) port. The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO) pins or the BTUART pins. Refer to information. When using the HWUART through the PCMCIA pins, they are driven at the same voltage level as the memory interface.
Page 574 — Break, parity, and framing error simulation • Fully prioritized interrupt system controls • Separate DMA requests for transmit and receive data services • Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) standard 17-2 Intel® PXA255 Processor Developer’s Manual –1 to...
Page 575: Example Uart Data Frame
17.3 Signal Descriptions Table 17-1 lists and describes each external signal that is connected to the UART module. The pins are connected to the PXA255 processor through GPIOs. Table 17-1. UART Signal Descriptions Name Type SERIAL INPUT – Serial data input to the receive shift register. In infrared mode, it is connected to the infrared Input receiver input.
Page 576: Example Nrz Bit Encoding – (0B0100 1011
The UART has a transmit FIFO and a receive FIFO each holding 64 characters of data. There are three separate methods for moving data into and out of the FIFOs: interrupts, polling, and DMA. 17-4 Figure 17-2 Intel® PXA255 Processor Developer’s Manual shows the data byte 0b 0100 1011 in...
Page 577: Transmit Interrupt
Transmit Data Service – The processor checks the transmit data request (LSR[TDRQ]) bit which is set when transmitter needs data. The processor can also check the transmitter empty (LSR[TEMT]) bit, which is set when the transmit FIFO and Transmit Holding register are empty. Intel® PXA255 Processor Developer’s Manual Hardware UART 17-5...
Page 578 If an error occurs when the receive FIFO trigger threshold has been reached, such that a receive DMA request is set, users need to wait for the DMA to finish the transfer before reading out the error bytes through programmed I/O. If not, FIFO underflow could occur. 17-6 Intel® PXA255 Processor Developer’s Manual...
Page 579: Autoflow Control
'1'. If a logic '0' is transmitted, the auto-baud circuit counts the zero as part of the start bit, resulting in an incorrect baud rate being programmed into the Divisor Latch Register Low (DLL) and Divisor Latch Register High (DLH) registers. Intel® PXA255 Processor Developer’s Manual Section 17.4.2.1.
Page 580: Slow Infrared Asynchronous Interface
The pulse for each zero bit must occur, even for consecutive bits with no edge between them. 17-8 for more information on auto-baud. Intel® PXA255 Processor Developer’s Manual Section 17.5.8). When the formula Section 17.5.3 can be programmed by...
Page 581: Ir Transmit And Receive Example
The RCVEIR and XMITIR bits in the Infrared Selection Register (ISR) must not be set at the same time (refer to Intel® PXA255 Processor Developer’s Manual shows an asynchronous transmission as it is sent from the UART. The Figure 17-4).
Page 582: Rbr Bit Definitions
Table 17-3, holds the next data byte(s) to be transmitted. Section 17.5.15). Transmit Holding Register (THR) reserved Description Intel® PXA255 Processor Developer’s Manual 17-19). Table PXA255 Processor Hardware UART Byte 0 PXA255 Processor Hardware UART Byte 0 –1. The baud rate generator output...
Page 583: Dll Bit Definitions
DMA controller do not service the receive FIFO at the same time. When a character timeout indication interrupt occurs, the processor must handle the data in the receive FIFO through programmed I/O. Intel® PXA255 Processor Developer’s Manual 14.7456 MHz ---------------------------------- 16xDivisor describe the DLL and DLH registers.
Page 584: Ier Bit Definitions
RECEIVER DATA AVAILABLE INTERRUPT ENABLE (Source IIR[IID]): RAVIE 0 = Receiver Data Available (trigger threshold reached) Interrupt disabled 1 = Receiver Data Available (trigger threshold reached) Interrupt enabled 17-12 Interrupt Enable Register (IER) reserved Description Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART...
Page 585: Interrupt Conditions
Bits Name 31:8 — reserved FIFO MODE ENABLE STATUS: FIFOES[1:0] — reserved Intel® PXA255 Processor Developer’s Manual Table Table 17-9. If two or more interrupts represented by Interrupt origin Interrupt Identification Register (IIR) reserved Description 00 – Non-FIFO mode is selected 01 –...
Page 586: Interrupt Identification Register Decode
Non-FIFO mode: Transmit Holding register empty FIFO mode: transmit FIFO has half or less than half data. Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART RESET Control — Reading the Line Status register. Non-FIFO mode – Reading the Receiver Buffer register.
Page 587: Fcr Bit Definitions
RESETTF completes the current transmission. 0 = Writing 0 has no effect 1 = The transmitter FIFO is cleared Intel® PXA255 Processor Developer’s Manual Interrupt SET/RESET Function Source Clear to send, data set ready, ring indicator, received line signal detect.
Page 588: Receive Fifo Occupancy Register (For)
17-16 FIFO Control Register (FCR) reserved Description Table 17-11, shows the number of bytes currently remaining in the receive FIFO Occupancy Register (FOR) reserved Description Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART PXA255 Processor Hardware UART Byte Count...
Page 589: Auto-Baud Control Register (Abr)
UART interrupts the processor with the auto-baud lock interrupt (IIR[ABL] – it has written the count value into the ACR. The value is written regardless of the state of the auto- baud UART program bit (ABR[ABUP]). Intel® PXA255 Processor Developer’s Manual Table 17-12, controls the functionality and options for auto-baud-rate Section 17.5.9).
Page 590: Lcr Bit Definitions
1 = Forces parity bit to be opposite of EPS bit value 17-18 Autobaud Count Register (ACR) Description Table 17-14 specifies the format for the asynchronous data communications Line Control Register (LCR) reserved Description Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART Count Value PXA255 Processor Hardware UART...
Page 591: Line Status Register (Lsr)
The LSR must be read before the erroneous character is read. LSR[4:1] bits are set until software reads the LSR. Section 17.4.2.3 This is a read-only register. Ignore reads from reserved bits. Intel® PXA255 Processor Developer’s Manual Line Control Register (LCR) reserved Description 00 –...
Page 592: Lsr Bit Definitions
0 = No break signal has been received 1 = Break signal received 17-20 Line Status Register (LSR) reserved Description empty (FCR[TIL]=1), or the UART is waiting for data (non-FIFO mode) Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART...
Page 593: Modem Control Register (Mcr)
The MCR also controls the loopback mode. Loopback mode must be enabled before the UART is enabled. This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits. Intel® PXA255 Processor Developer’s Manual Line Status Register (LSR) reserved...
Page 594: Mcr Bit Definitions
(nRTS and nDTR) are forced to their inactive state. • RTS = 1 forces CTS to 1 • RTS = 0 forces CTS to a 0 Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART...
Page 595: Msr Bit Definitions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reset ? Bits Name 31:5 — reserved Intel® PXA255 Processor Developer’s Manual Modem Control Register (MCR) reserved Description Table 17-17, provides the current state of the control lines from the modem or Modem Status Register (MSR)
Page 596: Scratchpad Register (Scr)
Description Table 17-18, has no effect on the UART. It is intended as a scratchpad register Scratchpad Register (SCR) reserved Description Intel® PXA255 Processor Developer’s Manual PXA255 Processor Hardware UART PXA255 Processor Hardware UART Table 17-19, controls IrDA functions...
Page 597: Isr Bit Definitions
Table 17-20 contains the register addresses for the HWUART. Table 17-20. HWUART Register Locations (Sheet 1 of 2) Register Addresses 0x4160_0000 0x4160_0000 0x4160_0004 Intel® PXA255 Processor Developer’s Manual Infrared Selection Register (ISR) reserved Description DLAB Bit Name Value HWRBR “Receive Buffer Register (RBR)”...
Page 598 HWABR “Auto-Baud Control Register (ABR)” HWACR “Auto-Baud Count Register (ACR)” HWDLL “Divisor Latch Registers (DLL and DLH)” HWDLH “Divisor Latch Registers (DLL and DLH)” Intel® PXA255 Processor Developer’s Manual Description (read only) (write only) (read/write) (read/write) (read only) (read only)
Page 599 Hardware UART Intel® PXA255 Processor Developer’s Manual 17-27...