Intel PXA255 Developer's Manual page 230

Memory Controller
Table 6-24. MSC0/1/2 Bit Definitions (Sheet 2 of 3)
0x4800_0008
0x4800_000C
0x4800_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
RRR1/3/5 RDN1/3/5
Reset 0 1 1 1 1 1
Bits Access
7:4
3
6-48
RDF1/3/5
1 1 1 1 1 1 0
Name
ROM delay first access.
RDF programmed RDF value interpreted
0-11
12
13
14
15
R/W RDFx<3:0>
Address to data valid for the first read access from all devices except VLIO
is equal to (RDFx + 2) memclks.
Address to data valid for subsequent read accesses to non-burst devices is
equal to (RDFx + 1) memclks.
nWE assertion for write accesses (which are non-burst) to all Flash is equal
to (RDFx + 1) memclks.
nOE (nPWE) assert time for each beat of read (write) is equal to (RDFx + 1)
memclks for Variable Latency I/O (nCS[5:0]). For Variable Latency I/O,
RDFx must be greater than or equal to 3.
ROM bus width
0 – 32 bits
1 – 16 bits
R/W RBWx For reset value for RBW0, see
This value must be programmed with all memory types including
Synchronous Static Memory.
This value must not change during normal operation.
MSC0
MSC1
MSC2
RT1/3/5 RDN0/2/4
0 0 0 0 1 1 1 1
Description
0-11
13
15
18
23
Section
Intel® PXA255 Processor Developer's Manual
Memory Controller
8 7 6 5 4 3
RDF0/2/4
1 1 1 1 1 1 1 *
6.8.
2 1 0
RT0/2/4
0 0 0