Pgsr0 Bit Definitions; Pgsr1 Bit Definitions - Intel PXA255 Developer's Manual

Clocks and Power Manager
Table 3-16. PGSR0 Bit Definitions
0x40F0_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0
Bits
[31:0]
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-17. PGSR1 Bit Definitions
0x40F0_0024
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0
Bits
[31:0]
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
3-32
0 0 0 0 0 0 0 0
Name
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
SSx
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
0 0 0 0 0 0 0 0
Name
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
SSx
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
PGSR0
0 0 0 0 0 0 0 0
Description
PGSR1
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
Clocks and Power Manager
8 7 6 5 4 3
0 0 0 0 0 0 0 0
Clocks and Power Manager
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0