Options And Settings For Boot Memory; Alternate Booting; Boot Time Defaults; Boot_Sel Definitions - Intel PXA255 Developer's Manual

Memory Controller
is deasserted or, as part of the sleep entry routine, the alternate master can be disabled. If necessary,
the alternate master can hold the bus until its transaction is completed. After the memory controller
has completed all outstanding transactions, it places SDRAM into self-refresh and allows the
processor to complete the sleep entry sequence.
Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is
asserted.
6.10

Options and Settings for Boot Memory

This section explains the settings that control Boot Memory configurations.
6.10.1

Alternate Booting

The processor allows six boot configurations. These configurations are determined by the three
BOOT_SEL(2:0) pins and are described in
pins on the Configuration registers at boot time is included in
Table 6-39. BOOT_SEL Definitions
2
0
0
0
0
1
1
1
1
6.10.2

Boot Time Defaults

The following sections provide information on boot time default parameters.
6.10.2.1 BOOT_DEF Read-Only Register (BOOT_DEF)
BOOT_DEF, shown in
the single package-type bit.
This is a read-only register. Ignore reads from reserved bits.
6-74
BOOT_SEL
1 0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Table 6-40, contains the boot-up values for the three BOOT_SEL pins and
Table 6-39. A description of the effect of these input
Section
Boot From...
Asynchronous 32-bit ROM
Asynchronous 16-bit ROM
reserved
reserved
1- 32-bit Synchronous Mask ROM (64 Mbit)
2- 16-bit Synchronous Mask ROMs = 32 bits (32 Mbit each)
1- 16-bit Synchronous Mask ROM (64 Mbit)
2- 16-bit Synchronous Mask ROMs = 32 bits (64 Mbit each)
1- 16-bit Synchronous Mask ROM (32 Mbit)
Intel® PXA255 Processor Developer's Manual
6.8.