Intel PXA255 Developer's Manual page 20

Contents
10-5 DLL Bit Definitions ...................................................................................................................10-8
10-6 DLH Bit Definitions ..................................................................................................................10-8
10-7 IER Bit Definitions....................................................................................................................10-9
10-8 Interrupt Conditions ...............................................................................................................10-10
10-9 IIR Bit Definitions ...................................................................................................................10-10
10-10 Interrupt Identification Register Decode ................................................................................10-11
10-11 FCR Bit Definitions ................................................................................................................10-12
10-12 LCR Bit Definitions ................................................................................................................10-14
10-13 LSR Bit Definitions.................................................................................................................10-15
10-14 MCR Bit Definitions ...............................................................................................................10-18
10-15 MSR Bit Definitions................................................................................................................10-20
10-16 SPR Bit Definitions ................................................................................................................10-21
10-17 ISR Bit Definitions..................................................................................................................10-24
10-18 FFUART Register Summary..................................................................................................10-26
10-19 BTUART Register Summary .................................................................................................10-26
10-20 STUART Register Summary .................................................................................................10-27
10-21 Flow Control Registers in BTUART and STUART.................................................................10-28
11-1 FICP Signal Description ..........................................................................................................11-1
11-2 ICCR0 Bit Definitions...............................................................................................................11-8
11-3 ICCR1 Bit Definitions.............................................................................................................11-10
11-4 ICCR2 Bit Definitions.............................................................................................................11-11
11-5 ICRD Bit Definitions...............................................................................................................11-12
11-6 ICSR0 Bit Definitions .............................................................................................................11-13
11-7 ICSR1 Bit Definitions .............................................................................................................11-15
11-8 FICP Register Summary........................................................................................................11-16
12-1 Endpoint Configuration ............................................................................................................12-2
12-2 USB States ..............................................................................................................................12-3
12-3 IN, OUT, and SETUP Token Packet Format ...........................................................................12-5
12-4 SOF Token Packet Format......................................................................................................12-5
12-5 Data Packet Format.................................................................................................................12-6
12-6 Handshake Packet Format ......................................................................................................12-6
12-7 Bulk Transaction Formats........................................................................................................12-7
12-8 Isochronous Transaction Formats ...........................................................................................12-7
12-9 Control Transaction Formats ...................................................................................................12-7
12-10 Interrupt Transaction Formats .................................................................................................12-8
12-11 Host Device Request Summary ..............................................................................................12-9
12-12 UDCCR Bit Definitions...........................................................................................................12-22
12-13 UDC Control Function Register .............................................................................................12-24
12-14 UDCCS0 Bit Definitions.........................................................................................................12-25
12-15 UDCCS1/6/11 Bit Definitions.................................................................................................12-27
12-16 UDCCS2/7/12 Bit Definitions.................................................................................................12-29
12-17 UDCCS3/8/13 Bit Definitions.................................................................................................12-31
12-18 UDCCS4/9/14 Bit Definitions.................................................................................................12-33
12-19 UDCCS5/10/15 Bit Definitions...............................................................................................12-34
12-20 UICR0 Bit Definitions.............................................................................................................12-37
12-21 UICR1 Bit Definitions.............................................................................................................12-38
12-22 USIR0 Bit Definitions .............................................................................................................12-39
12-23 USIR1 Bit Definitions .............................................................................................................12-41
12-24 UFNHR Bit Definitions ...........................................................................................................12-43
12-25 UFNLR Bit Definitions............................................................................................................12-44
xx Intel® PXA255 Processor Developer's Manual