Intel PXA255 Developer's Manual page 421

When software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT
transaction, it may take one of three courses of action, as appropriate for the chosen operating
model:
•
Configure the DMA engine and disable the EP4 interrupt to allow the DMA engine to handle
the transaction.
•
Enable the EP4 interrupt to allow the Megacell to directly handle the transaction.
•
Enable the SOF interrupt to handle the transaction on a frame count basis.
12.5.8.1 Software Enables the DMA
If software enables the DMA engine, use the following steps:
1. During the SETUP VENDOR command, software enables the DMA engine and sets the
UDCCS4[DME] bit. ISO packet sizes are not restricted, but a packet size of modulo 32 is
highly recommended efficiency.
a. If the packet size is between 32 and 256 bytes modulo 32, software determines the
number of descriptors needed and sets up a string of descriptors. Software sets the
interrupt bit for the appropriate descriptor.
b. If the packet size is between 32 bytes and 256 bytes, but not modulo 32 bytes, software
sets up a descriptor to receive each data packet, then reads the remaining data on each
UDCCS2[RSP] bit interrupt and sets up another descriptor.
c. If the packet size is less than 32 bytes, software must use interrupt mode.
2. The host PC sends a ISOC-OUT.
3. The DMA engine reads the data from the EP4 data FIFO (UDDR4).
4. Steps
5. If the software receives an EP4 interrupt it completes the following process:
a. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length
packet.
b. If UDCCS4[RNE] is set, the data packet was a short packet and software uses the
UDCWC4 count register to read the proper amount of data from the EP4 data FIFO
(UDDR4).
c. Software clears the UDCCS4[RPC] bit.
6. Return from interrupt.
12.5.8.2 Software Allows the Megacell to Handle the Transaction
If software allows the Megacell to handle the transaction:
1. During the SETUP VENDOR command, software clears the UDCCS4[DME] bit.
2. The host PC sends a ISOC-OUT and the UDC generates an EP4 Interrupt.
3. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet.
4. If UDCCS4[RNE] is set, software uses the UDCWC4 count register to read the proper amount
of data from the EP4 data FIFO (UDDR4).
5. Software clears the UDCCS4[RPC] bit.
Intel® PXA255 Processor Developer's Manual
2 and 3 repeat until all the data has been read from the host.
USB Device Controller
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