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Intel Manuals
Computer Hardware
PXA270
Optimization manual
Intel PXA270 Optimization Manual
Pxa27x processor family
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
Revision History
1 Introduction
About this Document
Related Documentation
High-Level Overview
Intel Xscale® Microarchitecture and Intel Xscale® Core
Pxa27X Processor Block Diagram
Intel Xscale® Microarchitecture Features
Intel® Wireless MMX™ Technology
Memory Architecture
Caches
External Memory Controller
Internal Memories
Processor Internal Communications
System Bus
Peripheral Bus
Peripherals in the Processor
Wireless Intel Speedstep® Technology
Intel Xscale® Microarchitecture Compatibility
Pxa27X Processor Performance Features
2 Microarchitecture Overview
Introduction
Intel Xscale® Microarchitecture Pipeline
General Pipeline Characteristics
Pipeline Organization
Intel Xscale® Microarchitecture RISC Superpipeline
Out of Order Completion
Use of Bypassing
Instruction Flow through the Pipeline
Pipelines and Pipe Stages
ARM* V5TE Instruction Execution
Pipeline Stalls
Main Execution Pipeline
F1 / F2 (Instruction Fetch) Pipestages
Execute (X1) Pipestages
Instruction Decode (ID) Pipestage
Register File / Shifter (RF) Pipestage
D1 and D2 Pipestage
Execute 2 (X2) Pipestage
Memory Pipeline
Multiply/Multiply Accumulate (MAC) Pipeline
Write-Back (WB)
Behavioral Description
Perils of Superpipelining
Intel® Wireless MMX™ Technology Pipeline
Execute Pipeline Thread
ID Stage
RF Stage
Intel® Wireless MMX™ Technology Pipeline Threads and Relation with Intel Xscale® Microarchitecture Pipeline
X1 Stage
X2 Stage
XWB Stage
Multiply Pipeline Thread
M1 Stage
M2 Stage
M3 Stage
MWB Stage
D1 Stage
D2 Stage
DWB Stage
Memory Pipeline Thread
3 System Level Optimization
Optimizing Frequency Selection
Memory System Optimization
Optimal Setting for Memory Latency and Bandwidth
External SDRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
Alternate Memory Clock Setting
Internal SRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
Page Table Configuration
Page Attributes for Data Access
Page Attributes for Instructions
Data Cache and Buffer Behavior When X = 1
Optimizing for Instruction and Data Caches
Increasing Instruction Cache Performance
Data Cache and Buffer Operation Comparison for Intel® SA-1110 and Intel Xscale
Round Robin Replacement Cache Policy
Code Placement to Reduce Cache Misses
Locking Code into the Instruction Cache
Increasing Data Cache Performance
Cache Configuration
Creating Scratch RAM in the Internal SRAM
Creating Scratch RAM in Data Cache
Reducing Memory Page Thrashing
Optimizing TLB (Translation Lookaside Buffer) Usage
Reducing Cache Conflicts, Pollution and Pressure
Using Mini-Data Cache
Optimizing for Internal Memory Usage
Buffer for Capture Interface
LCD Frame Buffer
Buffer for Context Switch
Increasing Preloads for Memory Performance
OS Acceleration
Scratch Ram
Optimization of System Components
Bandwidth and Latency Requirements for LCD
LCD Controller Optimization
Frame Buffer Placement for LCD Optimization
Arbitration Scheme Tuning for LCD
LCD Color Conversion HW
LCD Display Frame Buffer Setting
Arbiter Functionality
Determining the Optimal Weights for Clients
Optimizing Arbiter Settings
Dynamic Adaptation of Weights
Taking Advantage of Bus Parking
Peripheral Bus Split Transactions
Usage of DMA
Memory to Memory Performance Using DMA for Different Memories and Frequencies
4 Intel Xscale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Introduction
General Optimization Techniques
Conditional Instructions and Loop Control
Program Flow and Branch Instructions
Optimizing Complex Expressions
Bit Field Manipulation
Optimizing the Use of Immediate Values
Optimizing Integer Multiply and Divide
Effective Use of Addressing Modes
Instruction Scheduling for Intel Xscale® Microarchitecture and Intel® Wireless MMX™ Technology
Instruction Scheduling for Intel Xscale® Microarchitecture
Scheduling Loads
Increasing Load Throughput
Increasing Store Throughput
Scheduling Load Double and Store Double (LDRD/STRD)
Scheduling Load and Store Multiple (LDM/STM)
Scheduling Data-Processing
Scheduling Multiply Instructions
Scheduling SWP and SWPB Instructions
Scheduling MRS and MSR Instructions
Scheduling the MRA and MAR Instructions (MRRC/MCRR)
Scheduling Coprocessor 15 Instructions
Instruction Scheduling for Intel® Wireless MMX™ Technology
Increasing Load Throughput on Intel® Wireless MMX™ Technology
Scheduling the WMAC Instructions
Scheduling the TMIA Instruction
Scheduling the WMUL and WMADD Instructions
SIMD Optimization Techniques
Software Pipelining
General Remarks on Software Pipelining
Multi-Sample Technique
General Remarks on Multi-Sample Technique
Data Alignment Techniques
Porting Existing Intel® MMX™ Technology Code to Intel® Wireless MMX™ Technology
Intel® Wireless MMX™ Technology Instruction Mapping
Pxa27X Processor Mapping to Intel® Wireless MMX™ Technology and SSE
Unsigned Unpack Example
Signed Unpack Example
Interleaved Pack with Saturation Example
Optimizing Libraries for System Performance
Case Study 1: Memory-To-Memory Copy
Case Study 2: Optimizing Memory Fill
Case Study 3: Dot Product
Case Study 4: Graphics Object Rotation
Case Study 5: 8X8 Block 1/2X Motion Compensation
Intel® Performance Primitives
Instruction Latencies for Intel Xscale® Microarchitecture
Performance Terms
Branch Instruction Timings
Data Processing Instruction Timings
Multiply Instruction Timings
Saturated Arithmetic Instructions
Load/Store Instructions
Status Register Access Instructions
CP15 and CP14 Coprocessor Instructions
Miscellaneous Instruction Timing
Semaphore Instructions
Thumb* Instructions
Instruction Latencies for Intel® Wireless MMX™ Technology
Performance Hazards
Data Hazards
Resource Hazard
Execution Pipeline
Multiply Pipeline
Memory Control Pipeline
Coprocessor Interface Pipeline
Multiple Pipelines
5 High Level Language Optimization
C and C++ Level Optimization
Efficient Usage of Preloading
Preload Considerations
Preload Loop Limitations
Coding Technique with Preload
Array Merging
Cache Blocking
Loop Interchange
Loop Fusion
Loop Unrolling
Loop Conditionals
If-Else Versus Switch Statements
Nested If-Else and Switch Statements
Locality in Source Code
Choosing Data Types
Data Alignment for Maximizing Cache Usage
Placing Literal Pools
Global Versus Local Variables
Number of Parameters in Functions
Other General Optimizations
6 Power Optimization
Introduction
Optimizations for Core Power
Code Optimization for Power Consumption
Switching Modes for Saving Power
Normal Mode
Deep Idle Mode
Deep-Sleep Mode
Idle Mode
Sleep Mode
Standby Mode
Wireless Intel Speedstep® Technology Power Manager
System Bus Frequency Selection
Fast-Bus Mode
Half-Turbo Mode
Optimizations for Memory and Peripheral Power
Improved Caching and Internal Memory Usage
SDRAM Auto Power down (APD)
External Memory Bus Buffer Strength Registers
Peripheral Clock Gating
LCD Subsystem
Voltage and Regulators
Operating Mode Recommendations for Power Savings
Idle Mode
Normal Mode
Deep-Idle Mode
Deep-Sleep Mode
Sleep Mode
Standby Mode
Performance Checklist
Performance Optimization Tips
Power Optimization Guidelines
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Intel® PXA27x Processor Family
Optimization Guide
April, 2004
Order Number: 280004-001
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This manual is also suitable for:
Pxa271
Pxa272
Pxa273
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