Interrupts; S Controller Register Summary; Transmit And Receive Fifo Accesses Through The Sadr - Intel PXA255 Developer's Manual

Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR
Transmit Data
PCM Transmit FIFO
Right
31
14.7

Interrupts

The following SASR0 status bits, if enabled, interrupt the processor:
•
Receive FIFO Service DMA Request (RFS)
•
Transmit FIFO Service DMA Request (TFS)
•
Transmit Under-run (TUR)
•
Receive Over-run (ROR).
Note: For further details, see
2
14.8 I

S Controller Register Summary

All registers are word addressable (32 bits wide) and hence increment in units of 0x00004. All
I2SC registers are mapped in the address range of 0x4040_0000 through 0x4040_0080, as shown
in Table 14-12.
Intel® PXA255 Processor Developer's Manual
Processor/DMA
Write
TxEntry15
31
TxEntry3
TxFIFO
Written
TxEntry2
TxEntry1
TxEntry0
Left
16 15 0
Section 14.6.3.
Inter-Integrated-Circuit Sound (I2S) Controller
Processor/DMA
Read
SADR Register
0
RxFIFO
Read
Receive Data
RxEntry15
PCM Receive FIFO
RxEntry3
RxEntry2
RxEntry1
RxEntry0
Right Left
31 16 15
14-15
0