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Clocks and Power Manager
3.4.10
Power Mode Summary
Table 3-4
that occur when a Power Mode is exited. In the tables, an empty cell means that the power mode
skips that step.
Table 3-4. Power Mode Entry Sequence Table
1
Software writes a bit in CP14
2
The CPU waits until all instructions to be completed
3
Wake up sources are cleared and limited to GP[1:0]
4
The PM places GPIOs in their sleep states
5
The Memory Controller finishes all outstanding transactions
6
The Memory Controller places SDRAMs in self-refresh
7
The PLL is disabled
8
If OPDE and OOK bits are set, disable 3.6864 MHz oscillator
9
Internal Reset to most modules. nRESET_OUT asserted
10
PWR_EN is deasserted. Power is cut off
11
Power to most I/O pins is cut off
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
.
Table 3-5. Power Mode Exit Sequence Table (Sheet 1 of 2)
1
Wake up source or Interrupt is received
2
Power to I/O pins restored
3
PWR_EN is asserted
4
External power ramp
5
Enable 3.6864 MHz oscillator if OPDE and OOK are set
Wait for 3.6864 MHz oscillator to stabilize if OPDE and OOK
6
are set
7
Enable PLL with new frequency
8
Wait for PLL stabilization
9
Wait for internal stabilization
10
Clear CP14 bit
3-20
shows the actions that occur when a Power Mode is entered.
Table 3-6
shows the expected behavior for power supplies in each power mode.
Description of Action
Description of Action
Table 3-5
x
x
x
x
x
x
x
x
Intel® PXA255 Processor Developer's Manual
shows the actions
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
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