Intel PXA255 Developer's Manual page 40

System Architecture
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin Name Type
SDCLK[1] OCZ
SDCLK[2] OC
nCS[5]/
ICOCZ
GPIO[33]
nCS[4]/
ICOCZ
GPIO[80]
nCS[3]/
ICOCZ
GPIO[79]
nCS[2]/
ICOCZ
GPIO[78]
nCS[1]/
ICOCZ
GPIO[15]
nCS[0] ICOCZ
RD/nWR OCZ
RDY/
ICOCZ
GPIO[18]
L_DD[8]/
ICOCZ
GPIO[66]
L_DD[15]/
ICOCZ
GPIO[73]
MBGNT/
ICOCZ
GP[13]
MBREQ/
ICOCZ
GP[14]
PCMCIA/CF Control Pins
nPOE/
ICOCZ
GPIO[48]
nPWE/
ICOCZ
GPIO[49]
2-10
Signal Descriptions
SDRAM Clocks (output) Connect SDCLK[1] and
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
turned off via free running control register bits in the
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always deasserted upon reset.
Static chip selects. (output) Chip selects to static
memory devices such as ROM and Flash. Individually
programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
Static chip select 0. (output) Chip select for the boot
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
current transaction is a read or write.
Variable Latency I/O Ready pin. (input) Notifies the
memory controller when an external bus device is ready
to transfer data.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
LCD display data. (output) Transfers pixel information
from the LCD Controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller grant. (output) Notifies an external
device that it has been granted the system bus.
Memory Controller alternate bus master request.
(input) Allows an external device to request the system
bus from the Memory Controller.
PCMCIA output enable. (output) Reads from PCMCIA
memory and to PCMCIA attribute space.
PCMCIA write enable. (output) Performs writes to
PCMCIA memory and to PCMCIA attribute space. Also
used as the write enable signal for Variable Latency I/O.
Reset State
Driven Low
Driven Low
Pulled High -
Note[1]
Driven High
Driven Low
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Pulled High -
Note[1]
Intel® PXA255 Processor Developer's Manual
Sleep State
Driven Low
Driven Low
Note [4]
Note [4]
Holds last state
Note [3]
Note [3]
Note [3]
Note [3]
Note [3]
Note [5]
Note [5]