Intel PXA255 Developer's Manual page 11

14.3 Controller Operation ........................................................................................................14-3
14.3.1 Initialization .........................................................................................................14-3
14.3.2 Disabling and Enabling Audio Replay.................................................................14-4
14.3.3 Disabling and Enabling Audio Record ................................................................14-4
14.3.4 Transmit FIFO Errors ..........................................................................................14-5
14.3.5 Receive FIFO Errors ...........................................................................................14-5
14.3.6 Trailing Bytes ......................................................................................................14-5
14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-5
14.5 Data Formats ...................................................................................................................14-6
14.5.1 FIFO and Memory Format ..................................................................................14-6
14.5.2 I2S and MSB-Justified Serial Audio Formats......................................................14-6
14.6 Registers..........................................................................................................................14-8
14.6.1 Serial Audio Controller Global Control Register (SACR0) ..................................14-8
14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1) ..............14-10
14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-11
14.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-12
14.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-13
14.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-14
14.6.7 Serial Audio Data Register (SADR) ..................................................................14-14
14.7 Interrupts........................................................................................................................14-15
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14.8 I S Controller Register Summary ..................................................................................14-15
15 MultiMediaCard Controller..........................................................................................................15-1
15.1 Overview..........................................................................................................................15-1
15.2 MMC Controller Functional Description ...........................................................................15-4
15.2.1 Signal Description ...............................................................................................15-6
15.2.2 MMC Controller Reset ........................................................................................15-6
15.2.3 Card Initialization Sequence ...............................................................................15-6
15.2.4 MMC and SPI Modes..........................................................................................15-6
15.2.5 Error Detection....................................................................................................15-8
15.2.6 Interrupts.............................................................................................................15-8
15.2.7 Clock Control ......................................................................................................15-9
15.2.8 Data FIFOs .......................................................................................................15-10
15.3 Card Communication Protocol.......................................................................................15-12
15.3.1 Basic, No Data, Command and Response Sequence ......................................15-13
15.3.2 Data Transfer ....................................................................................................15-13
15.3.3 Busy Sequence.................................................................................................15-16
15.3.4 SPI Functionality ...............................................................................................15-17
15.4 MultiMediaCard Controller Operation ............................................................................15-17
15.4.1 Start and Stop Clock .........................................................................................15-17
15.4.2 Initialize .............................................................................................................15-17
15.4.3 Enabling SPI Mode ...........................................................................................15-17
15.4.4 No Data Command and Response Sequence..................................................15-18
15.4.5 Erase ................................................................................................................15-18
15.4.6 Single Data Block Write ....................................................................................15-18
15.4.7 Single Block Read ............................................................................................15-19
15.4.8 Multiple Block Write ..........................................................................................15-20
15.4.9 Multiple Block Read ..........................................................................................15-20
15.4.10 Stream Write .....................................................................................................15-21
15.4.11 Stream Read.....................................................................................................15-21
Intel® PXA255 Processor Developer's Manual
Contents
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