Pcm Transmit And Receive Operation; Mccr Bit Definitions - Intel PXA255 Developer's Manual

Figure 13-9. PCM Transmit and Receive Operation
Transmit Data
PCM Transmit FIFO
Right
31
13.8.3.9 Mic-In Control Register (MCCR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 13-15. MCCR Bit Definitions
Physical Address
4050_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:4
3 FEIE
2:0
13.8.3.10 Mic-In Status Register (MCSR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
Processor/DMA
TxEntry15
31
TxEntry3
TxEntry2
TxEntry1
TxEntry0
Left
16 15 0
MCCR Register
reserved
0 0 0 0 0 0 0
— reserved
FIFO Error Interrupt Enable (FEIE
This bit controls whether the occurrence of a receive FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the MCSR is set
1 = An interrupt will occur if bit 4 in the MCSR is set.
— reserved
Write
Processor/DMA
Read
PCDR Register
RxFIFO
TxFIFO
Read
Written
0 0 0 0 0 0 0 0
Description
AC'97 Controller Unit
Receive Data
RxEntry15
PCM Receive FIFO
0
RxEntry3
RxEntry2
RxEntry1
RxEntry0
Right Left
31 16 15
AC'97 Controller Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
0
2 1 0
0 0 0
13-27