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Table 6-15. Synchronous Static Memory External to Internal Address Mapping Options
# Bits
External Address pins at SXMEM RAS Time
Bank x
Row x
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Col x
Data
2x12x7x32
22 21 20 19 18 17 16 15 14 13 12 11 10 9
2x12x7x16
21 20 19 18 17 16 15 14 13 12 11 10 9
2x12x8x32
23 22 21 20 19 18 17 16 15 14 13 12 11 10
2x12x8x16
22 21 20 19 18 17 16 15 14 13 12 11 10 9
2x12x9x32
24 23 22 21 20 19 18 17 16 15 14 13 12 11
2x12x9x16
23 22 21 20 19 18 17 16 15 14 13 12 11 10
2x12x10x32
25 24 23 22 21 20 19 18 17 16 15 14 13 12
2x12x10x16
24 23 22 21 20 19 18 17 16 15 14 13 12 11
2x13x7x32
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22
2x13x7x16
22 21 20 19 18 17 16 15 14 13 12 11 10 9
2x13x8x32
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23
2x13x8x16
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22
2x13x9x32
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24
2x13x9x16
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23
2x13x10x16
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24
6.6.2
Synchronous Static Memory Mode Register Set
Configuration Register (SXMRS)
On power up, a MRS command that contains the default boot-up value is written to the external
memory if the system is configured to boot out of SMROM (see
SXMRS, shown in
in this register is placed directly on address lines MA<24:10> during the MRS command. Writing
to this register triggers a two-stage MRS command that is sent to the external synchronous static
memory. The first state issues an MRS command to banks 0 and 1. The second stage issues an
MRS command to banks 2 and 3. The corresponding chip select values are only asserted if the
memory banks are enabled via the SXCNFG register and the memory type is configured as
SMROM.
To write a new MRS value to a synchronous static memory, first enable and configure the memory
via the SXCNFG register, then write the SXMRS register. This register is only used for the value
written during the MRS command. All values in the SXCNFG register must be programmed
correctly to ensure proper device operation (refer to the external memory chip product
documentation for proper MRS encoding). Information programmed in the SXCNFG[CL] and
Intel® PXA255 Processor Developer's Manual
MA<24:10>
Table
6-16, is used to issue an MRS command to SMROM. The value written
External Address pins at SXMEM CAS Time
MA<24:10>
22 21
0
8
21 20
0
23 22
0
22 21
0
24 23
0
10 9
23 22
0
9
25 24
0
11 10 9
24 23
0
10 9
0
8 22 21
0
0
0
0
10 9
0
9
0
10 9
Section
Memory Controller
8
7
6
5
4
3
2
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
6.10.2). Otherwise,
6-37
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