Initialization - Intel PXA255 Developer's Manual

Receive FIFO entries are read through the PCDR, the MODR, or the Mic-in Data Register
(MCDR).
Note: After it is enabled, the ACUNIT requests the DMA to fill the transmit FIFO.
Note: The ACUNIT registers do not store the status of DMA requests or information regarding the
number of data samples in each FIFO. As a result, programmed I/O must not be used in place of
DMA requests for data transfers.
Only the DMA can access the FIFOs. The DMA controller accesses FIFO data in 8-, 16-, or 32-
byte blocks. The DMA request thresholds are not programmable.The ACUNIT makes a transmit
DMA request when the transmit FIFO has less than 32 bytes. The ACUNIT makes a receive DMA
request when the receive FIFO has 32 bytes or more. Regardless of burst size, the DMA descriptor
length must be a multiple of 32 bytes to prevent audio artifacts from being introduced onto the AC-
link.
The DMA controller responds to the following ACUNIT DMA requests:
•
PCM FIFO transmit and receive DMA requests made when the PCM transmit and receive
FIFOs are half full.
•
Modem FIFO transmit and receive DMA requests made when the modem transmit and receive
FIFOs are half full.
•
Mic-in receive DMA requests made when the Mic-in receive FIFO is half full.
13.6.1

Initialization

The AC'97 CODEC and ACUNIT are reset on power up. After power up, the nACRESET signal
remains asserted until the audio or modem driver sets the COLD_RST bit of the GCR to one.
During operation, clearing the COLD_RST bit to zero resets the ACUNIT and CODEC. To
initialize the ACUNIT follow theses steps:
1. Program the GPIO Direction register and GPIO Alternate Function Select register to assign
proper pin directions for the ACUNIT ports. Refer to
2. Set the COLD_RST bit of the GCR to one to deassert nACRESET. Until this is done, all other
registers remain in a reset state. Deasserting nACRESET has the following effects:
a. Frames filled with zeroes are transmitted because the transmit FIFO is still empty. This
situation does not cause an error condition.
b. The ACUNIT records zeroes until the CODEC sends valid data.
c. DMA requests are enabled.
3. Enable the Primary Ready Interrupt Enable and/or the Secondary Ready Interrupt Enable by
setting the PRIRDY_IEN bit and/or the SECRDY_IEN bit of the GCR to one.
4. Software enables DMA operation in response to primary and secondary ready interrupts.
5. The ACUNIT triggers transmit DMA requests. The DMA fills the transmit FIFO in response.
6. The ACUNIT continues to transmit zeroes until the transmit FIFO is half full. When it is half
full, valid transmit FIFO data is sent across the AC-link.
Note: When nACRESET is deasserted, a read to the CODEC Mixer register returns the type of hardware
that resides in the CODEC. If the CODEC is not present or if the AC'97 is not supported, the
Intel® PXA255 Processor Developer's Manual
AC'97 Controller Unit
Section 13.3 for details.
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